A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit ...A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.展开更多
Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detecti...Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.展开更多
Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of com...Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.展开更多
Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of te...Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.展开更多
探讨了低功耗设计在便携设备中的重要性,并结合互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)环形振荡器的设计从不同角度阐述低功耗设计的要点。首先,介绍了低功耗设计的概念、背景以及其在现代便携设备中的应...探讨了低功耗设计在便携设备中的重要性,并结合互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)环形振荡器的设计从不同角度阐述低功耗设计的要点。首先,介绍了低功耗设计的概念、背景以及其在现代便携设备中的应用。其次,讨论了动态功耗和静态功耗对电路的影响,提出相应的解决方法和优化措施。再次,从工艺调整和设计方法2个角度,详细介绍低功耗设计的方法。最后,结合具体的CMOS环形振荡器设计,展示了低功耗设计的实际应用和优势,为便携设备的高效、可靠运行提供了理论基础和技术支持。展开更多
A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM...A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.展开更多
为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法。...为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法。在宇宙环境中,卫星中的模拟CMOS集成电路存在CMOS半导体元器件阈值电压偏离、线性跨导减小、衬底的漏电流增加和转角1/f噪声幅值增加。所以提出了3种对模拟CMOS集成电路进行抗辐射加固的方法:1)抗辐射模拟CMOS集成电路的设计;2)抗辐射集成电路版图设计;3)单晶半导体硅膜(Silicon on Insulator,SOI)抗辐射工艺与加固设计。根据上面的设计方法研制了抗辐射加固模拟CMOS集成电路,可以取得较好的抗辐射效果。展开更多
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60536030,61036002,60776024,60877035 and 61036009)National High Technology Research and Development Program of China(Grant Nos.2007AA04Z329 and 2007AA04Z254)
文摘A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μm complementary metal-oxide-semiconductor technology. This device is capable of versatile working modes： it can emit visible to near infra-red （NIR） light （the spectrum ranges from 500 nm to 1000 nm） in reverse bias avalanche breakdown mode with working voltage between 8.35 V-12 V and emit NIR light （the spectrum ranges from 900 nm to 1300 nm） in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.
基金supported by the Plan for Science Innovation Talent of Henan Province(No.154100510007)the Natural and Science Foundation in Henan Province(No.162300410179)the Cultivation Foundation of Henan Normal University National Project(No.2017PL04)
文摘Complementary metal-oxide-semiconductor(CMOS) sensors can convert X-rays into detectable signals; therefore, they are powerful tools in X-ray detection applications. Herein, we explore the physics behind X-ray detection performed using CMOS sensors. X-ray measurements were obtained using a simulated positioner based on a CMOS sensor, while the X-ray energy was modified by changing the voltage, current, and radiation time. A monitoring control unit collected video data of the detected X-rays. The video images were framed and filtered to detect the effective pixel points(radiation spots).The histograms of the images prove there is a linear relationship between the pixel points and X-ray energy. The relationships between the image pixel points, voltage, and current were quantified, and the resultant correlations were observed to obey some physical laws.
文摘Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.
文摘Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.
文摘探讨了低功耗设计在便携设备中的重要性,并结合互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)环形振荡器的设计从不同角度阐述低功耗设计的要点。首先,介绍了低功耗设计的概念、背景以及其在现代便携设备中的应用。其次,讨论了动态功耗和静态功耗对电路的影响,提出相应的解决方法和优化措施。再次,从工艺调整和设计方法2个角度,详细介绍低功耗设计的方法。最后,结合具体的CMOS环形振荡器设计,展示了低功耗设计的实际应用和优势,为便携设备的高效、可靠运行提供了理论基础和技术支持。
基金The National Natural Science Foundation of China(No. 61106024)the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20090092120012)the Science and Technology Program of South east University (No. KJ2010402)
文摘A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.
文摘为研究宇宙辐射环境中航天器里的模拟互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)集成电路性能和各种效应,并在辐射效应所产生机制的基础上,从设计和工艺方面提出了模拟CMOS集成电路主要抗辐射加固设计方法。在宇宙环境中,卫星中的模拟CMOS集成电路存在CMOS半导体元器件阈值电压偏离、线性跨导减小、衬底的漏电流增加和转角1/f噪声幅值增加。所以提出了3种对模拟CMOS集成电路进行抗辐射加固的方法:1)抗辐射模拟CMOS集成电路的设计;2)抗辐射集成电路版图设计;3)单晶半导体硅膜(Silicon on Insulator,SOI)抗辐射工艺与加固设计。根据上面的设计方法研制了抗辐射加固模拟CMOS集成电路,可以取得较好的抗辐射效果。
