Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

Simulation and Design Optimization of Novel Microelectromechanical Digital-to-Analog Converter

A microelectromechanical Digital to Analog Converter (DAC) based on Weighted Gap (WG) principle is described,which is analogous to the weighed resistor DAC in electronic circuits.To convert the input of binary voltage to the output of analog displacement,the gaps are proposed to be employed as a scale factor.A finite element method is used to simulate the performance of the DAC.To reduce the error,the structure design is optimized and the maximum error of 0 002μm is obtained.

Energy-Efficient Large-Scale Antenna Systems with Hybrid Digital-Analog Beamforming Structure

A largescale antenna system （LSAS） with digital beamforming is expected to significantly increase energy efficiency （EE） and spectral efficiency （SE） in a wireless communication system. However, there are many challenging issues related to calibration, energy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digitalanalog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configuration in an N ＆#215; M beamforming structure, where N is the number of transceivers, M is the number of active antennas per transceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EESE curve, and show that the logscale EE scales linearly with SE along a slope of lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal （N, M） combination for optimizing EE. The results of numerical simulations are provided, and these results support our analysis.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

An Intermediate Frequency Acquisition Scheme for S-band Single Access Link of the Tracking and Data Relay Satellite System

A nonzero intermediate frequency (IF) likelihood acquisition scheme designed for S-band Single Access (SSA) link of China’s Tracking and Data Relay Satellite System (CTDRSS) is introduced. The received signal is downconverted to IF, and then direct sampled in IF using a 1-bit A/D. After the digitalization, the sampled data is detected using a hybrid likelihood acquisition scheme. Using this structure, large noise figure of the analog mixer or active filters, amplitude and phase imbalance between low-frequency in-phase and quandrature-phase channel can be avoided. An easy designing algorithm of the acquisition scheme is also derived. The performance and algorithm are verified by computer simulation.

Hardware Implementation and System Control Strategy of Videoconference System Based on Rec. H. 261

The design and realization of a videoconference system based on international recommendation are introduced in this paper, and the hardware implementation of video codec based on ITU-T H. 261 is briefly discussed. Furthermore, the buffer control method and the adaptive control strategy for quantization are proposed, which are adaptive and robust. This system can be operated under the transmission rate ranging from 128kb/s to 2Mb/s. With these strategies for the videoconference system, the high quality image is obtained. The time delay of the system is about half a second.

Design and Implementation of a Portable Computer Based Induction Motor Supervisory System

The aim of this research paper is to monitor an inductionmotor (single or three-phase) while working or running using a portable computer. Parameters measured include supply voltage, stator coli temperature and casing temperature. For the temperatures of both stator and casing, temperature sensors were used. The sensor senses the temperature and sends its output to the analogue to the digital integrated circuit for further processing. The supply voltage is also moni-tored by a circuit and integrated circuit. The project on completion was tested and the parameters displayed on the portable computer. The objectives of the project are: The supply system can measure the following parameters: supply voltage, stator coil temperature, casing temperature. Display the data on the PC screen with the possibility of settings to establish range, limits and alarm indicators when these are exceeded. The program should be able to save data of the log entry with time on a dedicated file as record for future analysis.

Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow

ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.

System Simulation Science and Simulation System Technology

This paper mainly discusses the following problems: the important meaning and special function of simulation system; the definition, contents and relationship of system and system simulation science; the definition and technology of simulation system and its equipments; and systematic description and exploration in relation to the developing trend of system simulation science and simulation system technology.

High Speed Electro-Absorption Modulators for Digital and Analog Optical Fiber Communications

An electro-absorption(EA)modulator is one of key components for optical fiber communications due to the high speed,small size,low voltage and integration ability with other semiconductor devices.A 40 Gb/s InGaAsP/InP multiplequantum-well(MQW)EA modulator monolithically integrated with a semiconductor optical amplifier(SOA)was fabricated for digital communications.The modulator capacitance was reduced to obtain 40 GHz bandwidth,and the SOA section helped reduce the insertion loss from 18 dB to 3 dB.InGaAlAs/InP MQW EA modulators have also been fabricated and characterized for analog optical fiber communications.A low driving voltage of 2.7 V and high spurious free dynamic range of 107 dB·Hz2/3 were estimated by static and dynamic measurements.

Design of Digital to Analog Converters with Arbitrary Radix

There are DAC structures available in the literature for radix r = 2, 3, and 4;but how they are arrived at is missing. No general structure is available for any radix r. The aim of the paper is, therefore, to fulfil these gaps. To start with, the design relations are derived for the simplest possible attenuator circuit when connected to a voltage source V and a series resistance R, such that the complete circuit offers the Thevenin resistance R. Spread relations for this attenuator are derived. An example when 3 such attenuators with different attenuation constants are connected in cascade is given. Interestingly, the two attenuators with attenuation factors 1/2 and 1/3 have the same spread of 2. A generalized attenuator is then obtained when N number of identical attenuators are connected in cascade. This is modified to derive a digital to analog converter for any radix r.

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.

Adaptive and Intelligent Digital Signal Processing for Improved Optical Interconnection

In recent years, explosively increasing data traffic has been boosting the con?tinuous demand of high speed optical interconnection inside or among data centers, high performance computers and even consumer electronics. To pursue the improved intercon?nection performance of capacity, energy efficiency and simplicity, effective approaches are demonstrated including particularly advanced digital signal processing (DSP) meth?ods. In this paper, we present a review about the enabling adaptive DSP methods for opti?cal interconnection applications, and a detailed summary of our recent and ongoing works in this field. In brief, our works focus on dealing with the specific issues for short-reach interconnection scenarios with adaptive operation, including signal-to-noise-ratio (SNR) limitation, level nonlinearity distortion, energy efficiency consideration and the de?cision precision.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

Optimization of Waste Gate Drive Circuit of Two-Stage Turbocharging System

A two stage turbocharging control system was proposed,in which the pressure regulator valve with a close-loop pressure adjusting function instead of a high speed on-off solenoid valve,is used as a driving mechanism of waste gate.A digital-analog（DA）conversion circuit based on pulse width modulation（PWM）generates one analog voltage signal required by the pressure regulating valve control.The principle of the DA conversion circuit was analyzed,meanwhile,the performance of the conversion circuit was improved by adopting a speed-up capacitor,which helps to increase the stability and responsiveness of the control voltage generated by the conversion circuit;the structure parameters of the circuit was optimized by simulation.After the optimization,the ripple wave of circuit output voltage was kept within16mV under the 12bit conversion accuracy,the conversion time of the circuit could be reduced to 4ms.The engine bench test show that the turbocharging boost pressure control system which adopted the circuit had a rather good stable control accuracy（the steady state within 0.8%）and dynamic response（the regulation time is less than 4s）.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Research on Digital and Analog Electronic Experiment Teaching Course Management based on UltraLab Network Experiment Platform

Digital circuit and analog circuit courses are basic courses for students of science and engineering universities. Among them,the practical courses are of great significance for students to master the knowledge of electronics. In order to make teachers teaching more efficiently and students studying more quickly,how to update the experimental course in teaching reform is the key point. This paper analyzing the present situation of teaching in the digital circuit and analog circuit courses,the teaching questions in universities. On the basis of it,the innovation measures of experimental teaching methods and contents are discussed. Our school tries to introduce the UltraLab network experiment platform,reform and optimize the teaching methods of related courses.And it’ s accelerating the construction and development of emerging engineering education’ s process,reducing effectively the teacher’s time for managing in equipment,improving the students’ ability to use instruments.

DIGITAL BACKGROUND CALIBRATION OF CAPACITOR MISMATCHES AND HARMONIC DISTORTION IN PIPELINED ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

Low Complexity Hybrid Wideband Beamforming for Millimeter-Wave Massive MIMO-OFDM Systems

In mmWave massive multiple-input multiple-output(MIMO)communication systems,the extension of low-complexity narrowband precoding schemes to be operated on wideband systems under frequency-selective channels remains an important challenge at the current time.This paper investigates a low complexity wideband hybrid precoding scheme for mmWave massive MIMO multicarrier systems under a single-user,fully-connected hybrid architecture.We show that the radio frequency(RF)precoding/combining vectors can be directly derived from the eigenvectors of the optimal fully-digital covariance matrix over all subcarriers in order to maximize the sum rate of spectral efficiency.We also suggest a new method that iteratively reduces the residual error between the covariance matrix and the sum of products of precoding matrices over all the subcarriers to improve the performance in the case where the number of RF chains is higher than the number of streams.The results of the simulation show that the proposed schemes’complexity is low compared to the present methods,and their performance can almost reach the upper bound achieved by the optimal full-baseband design.