The Numerical Analysis of Strain Behavior at Solder Joint and Interface of Flip Chip Package

The flip chip package is a kind of advanced electri ca l packages. Due to the requirement of miniaturization, lower weight, higher dens ity and higher performance in the advanced electric package, it is expected that flip chip package will soon be a mainstream technology. The silicon chip is dir ectly connected to printing circuit substrate by SnPb solder joints. Also, the u nderfill, a composite of polymer and silica particles, is filled in the gap betw een the chip and substrate around the solder joints to improve the reliabili ty of solder joints. When flip chip package specimen is tested with thermal cycl ing, the cyclic stress/strain response that exists at the underfill interfaces and solder joints may result in interfacial crack initiation and propagation. Therefore, the chip cracking and the interfacial delamination between underfill and chip corner have been investigated in many studies. Also, most researches h ave focused on the effect of fatigue and creep properties of solder joint induce d by the plastic strain alternation and accumulation. The nuderfill must have lo w viscosity in the liquid state and good adhesion to the interface after solidif ying. Also, the mechanical behavior of such epoxy material has much dependen ce on temperature in its glass transition temperature range that is usually cove red by the temperature range of thermal cycling test. Therefore, the materia l behavior of underfill exists a significant non-linearity and the assumption o f linear elastic can lack for accuracy in numerical analysis. Through numerical analysis, this study had some comparisons about the effect of linear and non -linear properties of underfill on strain behaviors around the interface of fli p chip assembly. Especially, the deformation tendency inside solder bumps could be predicted. Also, it is worthily mentioned that we have pointed out which comp onent of plastic strain, thus, either normal or shear, has dominant influence to the fatigue and creep of solder bump, which have not brought up before. About the numerical analysis to the thermal plastic strain occurs in flip chip i nterconnection during thermal cycling test, a commercial finite element software , namely, ANSYS, was employed to simulate the thermal cycling test obeyed by MIL-STD-883C. The temperatures of thermal cycling ranged from -55 ℃ to 125 ℃ with ramp rate of 36 ℃/min and a dwell time of 25 min at peak temperature. T he schematic drawing of diagonal cross-section of flip chip package composed of FR-4 substrate, silicon chip, underfill and solder bump was shown as Fig.1. Th e numerical model was two-dimensional (2-D) with plane strain assumption and o nly one half of the cross-section was modeled due to geometry symmetry. The dim ensions and boundary conditions of numerical model were shown in Fig.2. The symm etric boundary conditions were applied along the left edge of the model, and the left bottom corner was additional constrained in vertical direction to prevent body motion. The finite element meshes of overall and local numerical model was shown as Fig.3. In this study, two cases of material model were used to describe the material behavior of the underfill: the case1 was linear elastic model that assumed Young’s Modulus (E) and thermal expansion coefficient (CTE) were consta nt during thermal cycling; the case2 was MKIN model (in ANSYS) that had nonlinea r temperature-dependent stress-strain relationship and temperature-dependent CTE. The material model applied to the solder bump was ANAND model (in ANSYS) th at described time-dependent plasticity phenomenon of viscoplastic material. Bot h the FR-4 substrate and silicon chip were assumed as temperature-independent elastic material; moreover, FR-4 substrate is orthotropic while silicon chip is isotropic. From the comparison between numerical results of linear and nonlinear material a ssumption of underfill, (i.e. case1 and case2), the quantities of plastic strain around the interconnection from case1 are higher than that in case2. Thus, the linear

The TH Express high performance interconnect networks

Interconnection network plays an important role in scalable high performance computer （HPC） systems. The TH Express-2 interconnect has been used in MilkyWay-2 system to provide high-bandwidth and low-latency interprocessot communications, and continuous efforts are devoted to the development of our proprietary interconnect. This paper describes the state-of-the-art of our proprietary interconnect, especially emphasizing on the design of network interface. Several key features are introduced, such as user-level communication, remote direct memory access, offload collective operation, and hardware reliable end-to-end communication, etc. The design of a low level message passing infrastructures and an upper message passing services are also proposed. The preliminary performance results demonstrate the efficiency of the TH interconnect interface.