Interface charges boosted ultrafast lithiation in Li_4Ti_5O_12 revealed by in-situ electron holography

It is still a great challenge at present to combine the high rate capability of the electrochemical capacitor with the high electrochemical capacity feature of rechargeable battery in energy storage and transport devices. By studying the lithiation mechanism of Li_4Ti_5O_12 （LTO） using in-situ electron holography, we find that double charge layers are formed at the interface of the insulating Li_4Ti_5O_12 （Li_4） phase and the semiconducting Li_7Ti_5O_12 （Li_7） phase, and can greatly boost the lithiation kinetics. The electron wave phase of the LTO particle is found to gradually shrink with the interface movement, leaving a positive electric field from Li_7 to Li_4 phase. Once the capacitive interface charges are formed, the lithiation of the core/shell particle could be established within 10 s. The ultrafast kinetics is attributed to the built-in interface potential and the mixed Ti3＋/Ti4＋ sites at the interface that could be maximally lowering the thermodynamic barrier for Li ion migration.

Modeling of high permittivity insulator structure with interface charge by charge compensation

An analytical model of the power metal–oxide–semiconductor field-effect transistor(MOSFET)with high permittivity insulator structure(HKMOS)with interface charge is established based on superposition and developed for optimization by charge compensation.In light of charge compensation,the disturbance aroused by interface charge is efficiently compromised by introducing extra charge for maximizing breakdown voltage(BV)and minimizing specific ON-resistance(R_(on,sp)).From this optimization method,it is very efficient to obtain the design parameters to overcome the difficulty in implementing the R_(on,sp)–BV trade-off for quick design.The analytical results prove that in the HKMOS with positive or negative interface charge at a given length of drift region,the extraction of the parameters is qualitatively and quantitatively optimized for trading off BV and Ron,sp with JFET effect taken into account.

Novel high-voltage self-adaptive power device based on interface charge＊

This paper presents a novel high-voltage lateral double diffused metal-oxide semiconductor （LDMOS） with self- adaptive interface charge （SAC） layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer （EI） and increase breakdown voltage （BV）. The BV and EI of SAC LDMOS increase to 612 V and 600 V/tim from 204 V and 90.7 V/ttm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of r/which present the enhanced ability of interface charge on EI are defined and analysed.

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A new SOI power device with multi-region high-concentration fixed charge（MHFC） is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer（BOX）, by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.

Characterization of Interface Charge in NbAlO/AlGaN/GaN MOSHEMT with Different NbAlO Thicknesses

We investigate the influence of interface charge on electrical performance of NbAIO/A1GaN/GaN metal-oxide- semiconductor high electron mobility transistors （MOSHEMTs）. Through C-V measurements and simulations, we find that the donor-type interface fixed charge density Qit of 2.2 × 10^13 cm^-2 exists at the NbA10/A1GaN interface, which induces the shift of the threshold voltage much more negative. Furthermore, a trap density of approximately 0.43 × 10^13-1.14 ×10^13 cm^-2 eV^-1 is obtained at the NaA10/AlGaN interface, which is consistent with the frequency-dependent capacitance and conductance measurement results.

Cl^(-)ions accelerating interface charge transfer in a Si/In_(2)S_(3) Faradaic junction photocathode for solar seawater splitting

Photoelectrocatalytic seawater splitting is a promising low-cost method to produce green hydrogen in a large scale.The effects of Cl^(-)ions in seawater on the performance of a photoanode have been reported in previous studies.However,few researches have been done on the roles of Cl^(-)ions in a photocathode.Herein,for the first time,we find that Cl^(-)ions in the electrolyte improve the photocurrent of a Si/In_(2)S_(3) photocathode by 50% at-0.6 V_(RHE).An in-situ X-ray photoelectron spectroscopy(XPS)characterization combined with the time-of-flight secondary-ion mass spectrometry by simulating photoelectrochemical conditions was used to investigate the interface charge transfer mechanism.The results suggest that there is an In_(2)^(+3)S_(3-x)(OH)_(2x)layer on the surface of In_(2)S_(3) in the phosphate buffer solution(PBS)electrolyte,which plays a role as an interface charge transfer mediator in the Si/In_(2)S_(3) photocathode.The In_(2)^(+3)S_(3-x)(OH)_(2x)surface layer becomes In_(2)^(+3)S_(3-x)(Cl)_(2x)in the PBS electrolyte with NaCl and accelerates the charge transfer rate at the In_(2)S_(3)/electrolyte interface.These results offer a new concept of regulating interface charge transfer mediator to enhance the performance of photoelectrocatalytic seawater splitting for hydrogen production.

Modeling of tunneling current in ultrathin MOS structure with interface trap charge and fixed oxide charge

A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor （MOS） structure. In this model, the influences of interface trap charge （ITC） at the Si-SiO2 interface and fixed oxide charge （FOC） in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.

Finite size effect of ions and dipoles close to charged interfaces

The modified dipolar Poisson-Boltzmann （MDPB） equation, where the electrostatics of the dipolar interactions of solvent molecules and also the finite size effects of ions and dipolar solvent molecules are explicitly taken into account on a mean-field level, is studied numerically for a two-plate system with oppositely charged surfaces. The MDPB equation is solved numerically, using the nonlinear Multigrid method, for one-dimensional finite volume meshes. For a high enough surface charge density, numerical results of the MDPB equation reveal that the effective dielectric constant decreases with the increase of the surface charge density. Furthermore, increasing the salt concentration leads to the decrease of the effective dielectric constant close to the charged surfaces. This decrease of the effective dielectric constant with the surface charge density is opposite to the trend from the dipolar Poisson Boltzmann （DPB） equation. This seemingly inconsistent result is due to the fact that the mean-field approach breaks down in such highly charged systems where the counterions and dipoles are strongly attracted to the charged surfaces and form a quasi two-dimensional layer. In the weak-coupling regime with the electrostatic coupling parameter （the ratio of Bjerrum length to Gouy-Chapman length） Ξ 〈 1, where the MDPB equation works, the effective dielectric constant is independent of the distance from the charged surfaces and there is no accumulation of dipoles near the charged surfaces. Therefore, there are no physical and computational advantages for the MDPB equation over the modified Poisson-Boltzmann （MPB） equation where the effect of dipolar interactions of solvent dipoles is implicitly taken into account in the renormalised dielectric constant.

Charge Accumulation Characteristics of SF6-Epoxy Interface Under Negative Repetitive Nanosecond Pulses

Repetitve nanosecond impulses in gas-insulated metal-enclosed switchgear (GIS) are likely to trigger inside flashover. Interface charges on the spacer in GIS are considered one of the main factors damaging insulation performance and may be induced by overvoltage. For good understanding of insulation failures, accumulation characteristics of charges between SF6 and epoxy spacers under repetitive nanosecond impulses are investigated. It can be found under nanosecond impulses, the charge source in gas volume contributes to interface charge accumulation predominantly. Interface charges will be promoted by impulse number and amplitude. Accumulation processes are analyzed based on runaway electrons mechanism. When impulse amplitude exceeds a threshold value, discharge in the gas volume turns to a runaway mode. A runaway electron leads to the interface charge accumulation. Affected by motion of the runaway electrons, the potential peak gradually moves close to the grounded electrode when impulse amplitude is raised. Meanwhile, increasing impulse number can enhance surface potential. Surface potential will reach saturation eventually. However, memory effect of the repetitive impulse discharge makes the half-peak width of the surface potential at the interface change little. Design of GIS gas-solid insulations can refer to this research.

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

A NEW STRUCTURE AND ITS ANALYTICAL BREAKDOWN MODEL OF HIGH VOLTAGE SOI DEVICE WITH STEP UNMOVABLE SURFACE CHARGES OF BURIED OXIDE LAYER

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.

Time-domain Finite Element Method for Transient Electric Field and Transient Charge Density on Dielectric Interface

This paper is devoted to solving the transient electric field and transient charge density on the dielectric interface under the electroquasistatic(EQS)field conditions with high accuracy.The proposed method is suitable for both 2-D and 3-D applications.Firstly,the governing equations represented by scalar electric potential are discretized by the nodal finite element method(FEM)in space and the finite difference method in time.Secondly,the transient constrained electric field equation on the boundary(TCEFEB)is derived to calculate the normal component of the transient electric field intensities on the Dirichlet boundary and dielectric interface as well as the transient charge density on the dielectric interface.Finally,a 2-D numerical example is employed to demonstrate the validity of the proposed method.Furthermore,the comparisons of the numerical accuracy of the proposed method in this paper with the existing FEMs for electric field intensity and charge density on the dielectric interface are conducted.The results show that the numerical accuracy of the proposed method for calculating the normal component of transient electric field intensities on the Dirichlet boundary and dielectric interface as well as the transient charge density on the dielectric interface is close to that of nodal electric potential and an order of magnitude higher than those of existing FEMs.

Partial-SOI high voltage laterally double-diffused MOS with a partially buried n^+-layer

A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor （PSOI LDMOS） with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n＋-layer, which is partially buried on the bottom interface of the top silicon layer （PBNL PSOI LDMOS）. The undepleted interface n＋-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage （BV）. With the same thickness values of the top silicon layer （10 p.m） and buried oxide layer （0.375 μm）, the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%.

Investigation of radiation influences on electrical parameters of 4H-SiC VDMOS

The radiation influences on electrical parameters of4H-SiC vertical double-implanted metal-oxide-semiconductor field effect transistor( VDMOS) are studied. By simulations on SRIM software and SILVACO software, the electrical parameters shifts of the device with defects in different regions are observed. The results indicate that the defects in different regions induced by radiations lead to different degradations of the electrical parameters. Non-ionization bulk defects in the JFET region make the drain-source on-state resistance Rdson increase,and those near the impact ionization center make the breakdown voltage Vbreakdownincrease. Moreover,the radiationinduced SiC/SiO2 interface defects,known as negative interface charges or positive interface charges,influence the electrical parameters significantly as well. The positive interface charges along the SiC/SiO2 interface above the channel region lead to a decrease in threshold voltage Vth,Rdsonand Vbreakdown,while positive interface charges along the Si C/Metal interface above the main junction of the terminal only leads to the decrease in Vbreakdown. The negative interface charges along the SiC/SiO2 interface above the channel region can make Vth,Rdsonand Vbreakdownincrease.

Performance enhancement of ZnO nanowires/PbS quantum dot depleted bulk heterojunction solar cells with an ultrathin Al_2O_3 interlayer

Depleted bulk heterojunction （DBH） PbS quantum dot solar cells （QDSCs）, appearing with boosted short-circuit current density （Jsc）, represent the great potential of solar radiation utilization, but suffer from the problem of increased interfacial charge recombination and reduced open-circuit voltage （Voc）. Herein, we report that an insertion of ultrathin A1203 layer （ca. 1.2 A thickness） at the interface of ZnO nanowires （NWs） and PbS quantum dots （QDs） could remarkably improve the performance of DBH-QDSCs fabricated from them, i.e., an increase of Voc from 449 mV to 572 mV, J^c from 21.90 mA/cm2 to 23.98 mA/cm2, and power conversion efficiency （PCE） from 4.29% to 6.11%. Such an improvement of device performance is ascribed to the significant reduction of the interfacial charge recombination rate, as evidenced by the light intensity dependence on Jsc and Voc, the prolonged electron lifetime, the lowered trap density, and the enlarged recombination activation energy. The present research therefore provides an effective interfacial engineering means to improving the overall performance of DBH-QDSCs, which might also be effective to other types of optoelectronic devices with large interface area.

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n^+-layer

A novel silicon-on-insulator （SOI） high-voltage device based on epitaxy-separation by implantation oxygen （SIMOX） with a partial buried n＋-layer silicon-on-insulator （PBN SOI） is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumu- lated on the interface between top silicon layer and buried oxide layer （BOX） effectively enhance the electric field of the BOX （EI）, resulting in a high breakdown voltage （BV） for the device. For the same thicknesses of top silicon layer （10 μm） and BOX （0.375 μm）, the EI and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance （Ron,sp） adaptive buried electrode （ABE） silicon-on-insulator （SOI） power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide （BOX） layer, the negative drain voltage Vd is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than tile electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field EI and the breakdown voltage （BV） of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low Ron,sp is obtained. Furthermore, the structure also alleviates the self-heating effect （SHE）. The analytical model matches the simulation results.

Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers

A two-dimensional analytical model of double-gate（DG） tunneling field-effect transistors（TFETs） with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.

Synaptic a-Si:H/a-Ga_(2)O_(3) phototransistor inspired by the phototaxis behavior of organisms with all-optical and all-electrical stimulation modes

To improve neuromorphic computing performance,neuromorphic system components should mimic the behaviors of organic systems.In this study,a synaptic a-Si:H/a-Ga_(2)O_(3)phototransistor featuring all-optical and-electrical emulation is fabricated in a manner advantageous for complementary metal-oxide-semiconductor process integration.The phototransistor exhibits excitatory and inhibitory synaptic behaviors under stimulation by both optical and electrical signals.It mimics several essential synaptic functions,including excitatory postsynaptic current,inhibitory postsynaptic current,short-term memory,long-term memory,pairedpulse facilitation,and spike-timing-dependent plasticity.The optical and electrical modulation mechanisms are confirmed to arise from the a-Si:H/a-Ga_(2)O_(3) heterojunction structure and interface effects,and the device is shown to operate at low power in both optical and electrical modes.The all-optical weight modulation function is applied to the wavelength-differential behavior response of zebrafish,successfully mimicking the color perception process of the organism.Finally,to verify the translation of the optoelectrical-derived synaptic behaviors of the phototransistor into artificial neuromorphic computation,handwritten digit image recognition of the Modified National Institute of Standards and Technology dataset is performed by a convolutional neural network,with a demonstrated average learning accuracy of 98.46%.These findings verify the applicability of the synaptic a-Si:H/a-Ga_(2)O_(3) phototransistor in neuromorphic computing.