Memory limitations are always a focus of computer architecture. The live range aware cache （LIRAC） offers a way to reduce memory access using live range information. In the LIRAC system, scratch data need not be wri...Memory limitations are always a focus of computer architecture. The live range aware cache （LIRAC） offers a way to reduce memory access using live range information. In the LIRAC system, scratch data need not be written back if the data will no longer be used. Three kinds of software support developed for LIRAC architecture use compiler analyses, binary analyses, and trace analyses. Trace analysis results show that LIRAC can eliminate 29% of cache write-backs on average and up to 83% in the best case for the SPEC CPU 2000 benchmark. These software techniques can show the feasibility and potential benefit of the LIRAC architecture.展开更多
基金Supported by the National Natural Science Foundation of China (No. 60673145)the Basic Research Foundation of Tsinghua Na-tional Laboratory for Information Science and Technology (TNList)+1 种基金the Intel/University Sponsored Research, the National Key Basic Research and Development (973) Program of China (No. 2006CB303100)the IBM China Research Laboratory
文摘Memory limitations are always a focus of computer architecture. The live range aware cache （LIRAC） offers a way to reduce memory access using live range information. In the LIRAC system, scratch data need not be written back if the data will no longer be used. Three kinds of software support developed for LIRAC architecture use compiler analyses, binary analyses, and trace analyses. Trace analysis results show that LIRAC can eliminate 29% of cache write-backs on average and up to 83% in the best case for the SPEC CPU 2000 benchmark. These software techniques can show the feasibility and potential benefit of the LIRAC architecture.
