应用于高速图像传感器的高线性度Latch ADC

针对高速应用设备对CMOS图像传感器高速、高线性度的要求,本文在传统SS ADC(Single Slope ADC,单斜模数转换器)的基础上,实现了一款应用于图像传感器的Latch ADC,工作频率达到了600 MHz。Latch ADC可以多列像素共用一个Gray Code计数器,并通过Latch结构快速锁定和存储数据,实现了SS ADC中Counter和SRAM的功能。本文采用110 nm工艺,实现了一种高速12位Latch ADC。经过仿真验证,本文的Latch ADC具有高线性度,每次转换的周期为7.094μs,平均功率为180.3μW,转换功耗为1.279 nJ.

基于高斯滤波和AKAZE-LATCH的图像匹配算法

针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

薄膜全耗尽SOI MOSFET单晶体管Latch效应

本文在详细分析各种不同条件下全耗尽ＭＯＳＦＥＴ单晶体管Ｌａｔｃｈ效应测试结果的基础上，较为详细地讨论了单晶体管Ｌａｔｃｈ效应的物理机理，发现单管Ｌａｔｃｈ效应与ＭＯＳＦＥＴ的寄生双极晶体管有着极其密切的关系，最后还给出了相应的改进措施。

Comparative research on “high currents” induced by single event latch-up and transient-induced latch-up

By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.

平板显示器功率驱动芯片的Latch-up及克服方法

详细分析了平板显示器驱动芯片中的Latch-up现象,在此基础上采用了一种克服Latch-up的方法:在低压部分增加多子保护环,在高低压之间增加少子保护环。借助TCAD软件详细研究了少子环位置及宽度对抗Latch-up效果的影响。实验结果证明,采用该方法可以有效地克服功率集成电路的Latch-up现象。

基于积分图的LATCH算法改进

LATCH(基于机器学习的三像素块描述子)在原有局部二值描述子的基础上通过将二像素块比较改为三像素块提升了局部二值描述子的准确率,但提高准确率的同时带来了更大的时耗,在研究LATCH以及其他二值描述子的基础上,借鉴积分图在目标检测中的应用,将积分图的思想应用在改进LATCH描述子中,减少了LATCH描述子中各像素块内的重复计算量.实验证明,改进算法的描述子计算时间较原算法缩减了30%–40%,而配准精度与原算法保持相近.

Oracle中的Latch和Lock

本文描述了Latch和Lock的原理、分类、相关视图以及相应的重要SQL语句。

基于BRISK-LATCH的喀斯特山区无人机影像匹配算法

针对BRISK算法在喀斯特山区无人机影像匹配中存在耗时长、正确匹配点数较少的问题,该文提出一种基于BRISK检测子和LATCH描述符的喀斯特山区无人机影像匹配算法,即利用BRISK检测子对影像进行特征点检测,利用LATCH描述符描述特征点,并采用结合最小距离的FLANN算法进行粗匹配,最后利用RANSAC算法对影像进行精匹配,剔除粗匹配中的错误匹配点对。实验结果表明:该算法的匹配总数和正确点数是SIFT和AKAZE算法的2倍以上,单点平均耗时是二者的7%~80%;与BRISK算法相比,在匹配总数减少5%的情况下,该算法的正确点数增加了30%以上,单点平均耗时减少50%以上。

LATCH母乳喂养评估表在产妇住院期纯母乳喂养实践中的应用

目的探究LATCH母乳喂养评估表在提高产妇住院期纯母乳喂养率的效果。方法选择2019年5月—2019年11月在本院产科分娩且母婴同室的400例产妇作为研究对象,根据随机数字表法分为对照组200例和观察组200例,对照组采用常规的母乳喂养指导方法进行指导,观察组在常规母乳喂养指导前应用LATCH母乳喂养评估表进行评估,根据评估结果进行个性化的母乳喂养指导,比较两组产妇在住院期间的纯母乳喂养率、乳头皲裂发生率、对护理工作的满意度。结果观察组产妇住院期间纯母乳喂养率明显高于对照组,差异有统计学意义(P<0.01);观察组产妇乳头皲裂发生率明显低于对照组,差异有统计学意义(P<0.05);两组产妇对护理工作满意度有统计学意义(P<0.05)。结论应用LATCH母乳喂养评表可以降低产妇乳头皲裂发生率,提高产妇住院期纯母乳喂养率以及产妇对护理工作满意度。

CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。

产后早期产妇母乳喂养知识LATCH评分现状及其影响因素

目的 了解产后早期产妇母乳喂养知识、母乳喂养情况及影响因素。方法 于2018年6月至2019年2月在上海市同济大学附属第一医院对产后48~72小时的1 147名住院产妇采用母乳喂养知识问卷和LATCH量表展开横断面调查,并采用单因素分析和多元线性回归分析分析其影响因素。结果 产后48~72小时产妇母乳喂养知识平均得分为(13.42±2.29)分。多元线性回归显示,产妇年龄、学历、职业、户籍、有无接受母乳喂养教育是母乳喂养知识掌握的影响因素(P<0.05)。产后48~72小时产妇LATCH评分为(7.85±1.29)分。多元线性回归显示,产妇胎次及分娩方式是LATCH评分的影响因素(P<0.05)。结论 产后早期,应针对年龄小、文化程度低、未接受过母乳喂养教育的产妇,给与强化母乳喂养知识和喂养的健康教育;对于初产妇及剖宫产产妇,需密切注意其母乳喂养执行情况,及时介入干预。

Wear Characteristics of the Nuclear Control Rod Drive Mechanism(CRDM)Movable Latch Serviced in High Temperature Water

The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mechanism of each claw surface is not clear.In this paper,a detailed degradation analysis was carried out on each claw surface of movable latch combined with wear result and worn morphology.Results indicate that the boundary of carbide is preferred for corrosion because carbide presents a nobler Volta potential compared to the metal matrix or boundary region.Due to the oscillation of drive shaft between the claw surfaces of movable latch,the dominant wear mechanism on the upper surface of claw(USC)and lower surface of claw(LSC)is plastic deformation caused by impact wear.Mechanical impact wear will cause the fragmentation of carbides because of the high hardness and low ductility of carbides.Corrosion promotes the broken carbides to fall off from the metal matrix.The generated fine carbides(abrasive particles)cause extra abrasive wear on USC when the movable brings the drive shaft upward or downward.As a result,USC has a higher wear volume than LSC.This research proposes a method to evaluate the wear on the whole movable latches using a 3D full-size scanner.

基于Latch的CMOS动态比较器的研究

动态比较器具有高速和低功耗的优点,是现代集成电路中的重要单元。本文简单介绍了基于latch的CMOS动态比较器的基本工作原理以及国内外最新研究进展;分析了几种新型动态比较器的性能。

Investigation on latch-up susceptibility induced by high-power microwave in complementary metal–oxide–semiconductor inverter

The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.

The Performance of a Novel Latching-Type Electromagnetic Actuator for Single-Port Laparoscopic Surgery

This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim of this actuator is to allow these instruments to become articulated with a push of a button in order to provide the optimum angulation required during SLS operations. This new actuator is comprised of electromagnetic coil elements, soft magnetic frames and a permanent magnet. Unlike conventional electromagnetic actuators, latching-type electromagnetic actuators could maintain their positions at either end of the actuation stroke without any power application requirement. In the current design, magnetic attraction forces initiated between the permanent magnet and the magnetic frame are utilised to lock the position of the actuator whilst a certain angulation position of the actuator is achieved as a result of the magnetic repulsion forces established between the permanent magnet and the coil elements. The performance of the new actuator in terms of the output force, maximum angulation and patient’s safety, was evaluated experimentally and the results were found to compare well with those acquired numerically using finite element methods. This actuator was seen to exhibit sufficient actuation forces and hence, it was capable of providing adaptable angulation characteristics for SLS tools. Finally, thermal evaluation of the actuator’s operation was conducted, which was found to be within safety limits specified by clinicians.

系统共地引发LATCH-UP及应对措施

每一个系统都有自己的VDD、GND,信号都是相对本系统的GND而言。在某些特殊场合,系统间信号传输切换伴随着"共地"的过程,在这样的过程中若两个GND之间的电位不同,就会在两个不同的GND之间发生能量交换。如果两者电位相差很大,这种能量交换所发生的冲击可能会诱发系统中集成电路内部发生LATCH-UP。文中对这种特殊使用场合发生的LATCH-UP现象进行了描述,并通过对这种LATCH-UP现象的实验、分析,提出抑制发生这种LATCH-UP的措施。

THE DESIGN OF THE HIGH SPEED AND HIGH PRECISION LATCHING VOLTAGE COMPARATOR ZJ03

The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.

Application of the Latching Control System on the Power Performance of a Wave Energy Converter Characterized by Gearbox,Flywheel,and Electrical GeneratorGustavor

The latching control represents an attractive alternative to increase the power absorption of wave energy converters(WECs)by tuning the phase of oscillator velocity to the wave excitation phase.However,increasing the amplitude of motion of the floating body is not the only challenge to obtain a good performance of the WEC.It also depends on the efficiency of the power take-off system(PTO).This study aims to address the actual power performance and operation of a heaving point absorber with a direct mechanical drive PTO system controlled by latching.The PTO characteristics,such as the gear ratio,the flywheel inertia,and the electric generator,are analyzed in the WEC performance.Three cylindrical point absorbers are also considered in the present study.A wave-to-wire model is developed to simulate the coupled hydro-electro-mechanical system in regular waves.The wave energy converter(WEC)performance is analyzed using the potential linear theory but considering the viscous damping effect according to the Morison equation to avoid the overestimated responses of the linear theory near resonance when the latching control system is applied.The latching control system increases the mean power.However,the increase is not significant if the parameters that characterize the WEC provide a considerable mean power.The performance of the proposed mechanical power take-off depends on the gear ratio and flywheel.However,the gear ratio shows a more significant influence than the flywheel inertia.The operating range of the generator and the diameter/draft ratio of the buoy also influence the PTO performance.

A novel method of optimizing latch comparators

A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.