The Performance of a Novel Latching-Type Electromagnetic Actuator for Single-Port Laparoscopic Surgery

This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim of this actuator is to allow these instruments to become articulated with a push of a button in order to provide the optimum angulation required during SLS operations. This new actuator is comprised of electromagnetic coil elements, soft magnetic frames and a permanent magnet. Unlike conventional electromagnetic actuators, latching-type electromagnetic actuators could maintain their positions at either end of the actuation stroke without any power application requirement. In the current design, magnetic attraction forces initiated between the permanent magnet and the magnetic frame are utilised to lock the position of the actuator whilst a certain angulation position of the actuator is achieved as a result of the magnetic repulsion forces established between the permanent magnet and the coil elements. The performance of the new actuator in terms of the output force, maximum angulation and patient’s safety, was evaluated experimentally and the results were found to compare well with those acquired numerically using finite element methods. This actuator was seen to exhibit sufficient actuation forces and hence, it was capable of providing adaptable angulation characteristics for SLS tools. Finally, thermal evaluation of the actuator’s operation was conducted, which was found to be within safety limits specified by clinicians.

Application of the Latching Control System on the Power Performance of a Wave Energy Converter Characterized by Gearbox,Flywheel,and Electrical GeneratorGustavor

The latching control represents an attractive alternative to increase the power absorption of wave energy converters(WECs)by tuning the phase of oscillator velocity to the wave excitation phase.However,increasing the amplitude of motion of the floating body is not the only challenge to obtain a good performance of the WEC.It also depends on the efficiency of the power take-off system(PTO).This study aims to address the actual power performance and operation of a heaving point absorber with a direct mechanical drive PTO system controlled by latching.The PTO characteristics,such as the gear ratio,the flywheel inertia,and the electric generator,are analyzed in the WEC performance.Three cylindrical point absorbers are also considered in the present study.A wave-to-wire model is developed to simulate the coupled hydro-electro-mechanical system in regular waves.The wave energy converter(WEC)performance is analyzed using the potential linear theory but considering the viscous damping effect according to the Morison equation to avoid the overestimated responses of the linear theory near resonance when the latching control system is applied.The latching control system increases the mean power.However,the increase is not significant if the parameters that characterize the WEC provide a considerable mean power.The performance of the proposed mechanical power take-off depends on the gear ratio and flywheel.However,the gear ratio shows a more significant influence than the flywheel inertia.The operating range of the generator and the diameter/draft ratio of the buoy also influence the PTO performance.

THE DESIGN OF THE HIGH SPEED AND HIGH PRECISION LATCHING VOLTAGE COMPARATOR ZJ03

The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.

应用于高速图像传感器的高线性度Latch ADC

针对高速应用设备对CMOS图像传感器高速、高线性度的要求,本文在传统SS ADC(Single Slope ADC,单斜模数转换器)的基础上,实现了一款应用于图像传感器的Latch ADC,工作频率达到了600 MHz。Latch ADC可以多列像素共用一个Gray Code计数器,并通过Latch结构快速锁定和存储数据,实现了SS ADC中Counter和SRAM的功能。本文采用110 nm工艺,实现了一种高速12位Latch ADC。经过仿真验证,本文的Latch ADC具有高线性度,每次转换的周期为7.094μs,平均功率为180.3μW,转换功耗为1.279 nJ.

A feedback latching controller for two-body wave energy converters under irregular wave conditions

Latching control is considered to be an effective way to improve the energy absorption of a wave energy converter(WEC).Recently, a latching control method was realized in a hydraulic power take-off(PTO) system and was demonstrated to be effective in one-body WECs. However, the effectiveness of latching control for two-body WECs still needs to be tested. In this paper, a feedback latching controller is proposed for a conceptual two-body WEC. In this conceptual design, a permanent-magnet linear generator(PMLG) is adopted as the PTO system, and a pure water hydraulic cylinder system is designed for performing the latching control. A feedback control strategy based on the measurement of latching force is established, formulated and tested numerically under realistic irregular wave conditions. The effects of the wave peak period and the PTO damping coefficient on the effectiveness of the latching control is also investigated. The results indicate that the proposed feedback latching control is effective for improving the annual power absorption of the two-body WEC. Furthermore, compared to another latching control,the proposed control is more practical because it does not require any knowledge of the wave conditions or the dynamics of the whole WEC system.

舌系带成型术对舌系带过短患儿母乳喂养的影响

目的:探讨舌系带成型术对舌系带过短患儿母乳喂养的影响。方法:选取某三级甲等综合医院2019—2021年113例母乳喂养的舌系带过短患儿,根据是否接受舌系带成型术分为观察组和对照组,其中观察组60例,对照组53例。评估两组患儿布里斯托尔舌评估工具(Bristol Tongue Assessment Tool, BTAT)评分,其中观察组包括术前、术后24 h、术后48 h评分;同时对两组患儿、产妇进行术前、术后24 h、术后48 h的母乳喂养评估表(LATCH)评分、含接评分、乳头疼痛评分(VAS评分)比较(观察组术后24、48 h时,同期收集对照组对应指标)。结果:观察组术前BTAT评分低于对照组(t=3.946,P<0.05),术后24 h、48 h BTAT评分高于对照组,且均高于观察组术前(t=10.536,t=13.555,均P<0.05);两组术前LATCH评分差异无统计学意义,观察组术后24、48 h LATCH评分均高于对照组(t=6.574,t=13.244,均P<0.05);观察组术前含接评分低于对照组(t=12.563,P<0.05),观察组术后24 h含接评分高于对照组(t=12.520,P<0.05),但术后48 h两组含接评分差异无统计学意义(t=0.051,P=0.822);两组术前产妇VAS评分差异无统计学意义(t=2.855,P=0.092),观察组术后24、48 h产妇VAS评分均低于对照组(t=4.991,t=9.398,均P<0.05);结论:经多学科团队合作统一评估路径对出生48 h内新生儿进行舌系带问题筛查,并对舌系带过短者行舌系带成型术,可明显改善舌系带过短患儿的舌头活动功能,促进患儿有效含接,改善产妇母乳喂养乳头疼痛感,提高婴幼儿母乳喂养质量,对后续母乳喂养体验和持续时间具有重要作用。

基于高斯滤波和AKAZE-LATCH的图像匹配算法

针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Gate-grounded n-channel metal-oxide-semiconductor(GGNMOS)devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction,easy triggering,and low power dissipation.We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies.This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground,and thus should be urgently analyzed and resolved.Transmission-linepulse,human-body-modal,and light-emission tests were performed to explore the root cause.

一种高精度动态CMOS比较器的设计与研制

比较器的设计对于A/D、D/A转换器的精度至关重要。为满足14位高分辨率A/D转换器的需要,设计了一种高精度动态CMOS比较器,采用二级差分比较和一级动态正反馈latch结构实现了高比较精度。预增益和Latch级的应用降低了功耗。设计中充分考虑了工艺离散性和使用环境温度与电源变化的影响,保证了成品率和电路在变化工作环境下性能指标的实现。仿真结果表明,设计的高速动态比较器LSB(Least Significant Bit)为±0.15mV,输入动态范围为VSS^VDD(VSS为地电压,VDD为电源电压),相应于14位比较精度。功耗6.28mW,工作频率3.6MHz。电路用0.6μm双层金属、双层多晶硅CMOS工艺实现。

一种新型高效容错体系结构的研究与实现

由于辐射而在电路的时序逻辑部分和组合逻辑部分产生的逻辑软错误已经逐渐成为阻碍系统可靠性和稳定性的主要威胁。提出了一种结合了基于主/从latch设计和改进的时间冗余策略两种技术的容错体系结构,通过ISCAS′89测试基准电路进行验证并对实验结果的分析发现,该容错体系结构获得了很高的容错性能。

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

A 1 ：2 demultiplexer is designed and realized in standard 0. 18μm CMOS technology. A novel high-speed and low-voltage latch is used to realize the core circuit cell. Compared to the traditional source-coupled FET logic structure latch, its power supply voltage is lower and the speed is faster. In addition, the negative feedback is used in the buffer circuit to widen its bandwidth. Measurement results show that the chip can work at the data rate of 20Gb/ s. The supply voltage is 1.8V and the current,including the buffer circuit, is 72mA.

薄膜全耗尽SOI MOSFET单晶体管Latch效应

本文在详细分析各种不同条件下全耗尽ＭＯＳＦＥＴ单晶体管Ｌａｔｃｈ效应测试结果的基础上，较为详细地讨论了单晶体管Ｌａｔｃｈ效应的物理机理，发现单管Ｌａｔｃｈ效应与ＭＯＳＦＥＴ的寄生双极晶体管有着极其密切的关系，最后还给出了相应的改进措施。

基于积分图的LATCH算法改进

LATCH(基于机器学习的三像素块描述子)在原有局部二值描述子的基础上通过将二像素块比较改为三像素块提升了局部二值描述子的准确率,但提高准确率的同时带来了更大的时耗,在研究LATCH以及其他二值描述子的基础上,借鉴积分图在目标检测中的应用,将积分图的思想应用在改进LATCH描述子中,减少了LATCH描述子中各像素块内的重复计算量.实验证明,改进算法的描述子计算时间较原算法缩减了30%–40%,而配准精度与原算法保持相近.

基于改进AKAZE算法的无人机影像匹配

针对如何稳定、高效、精确、高精度地进行无人影像匹配,提出一种改进的AKAZE算法。该算法首先利用AKAZE算法构造非线性尺度空间进行特征点检测;然后利用LATCH描述符对获取的特征点进行描述;接着利用Hamming距离作为相似性测度对特征点进行K近邻匹配,并采用比值提纯法进行粗匹配;最后,利用随机抽样一致(RANSAC)算法并结合均方根误差(RMSE)进行约束对粗匹配结果进行过滤,剔除错误匹配,得到精确匹配结果。实验结果表明,该算法在保持较高准确率、亚像素级匹配精度的同时具有较好的时间效率,且其对亮度、图像模糊以及压缩等变化具有较好的稳定性。

Oracle中的Latch和Lock

本文描述了Latch和Lock的原理、分类、相关视图以及相应的重要SQL语句。

基于BRISK-LATCH的喀斯特山区无人机影像匹配算法

针对BRISK算法在喀斯特山区无人机影像匹配中存在耗时长、正确匹配点数较少的问题,该文提出一种基于BRISK检测子和LATCH描述符的喀斯特山区无人机影像匹配算法,即利用BRISK检测子对影像进行特征点检测,利用LATCH描述符描述特征点,并采用结合最小距离的FLANN算法进行粗匹配,最后利用RANSAC算法对影像进行精匹配,剔除粗匹配中的错误匹配点对。实验结果表明:该算法的匹配总数和正确点数是SIFT和AKAZE算法的2倍以上,单点平均耗时是二者的7%~80%;与BRISK算法相比,在匹配总数减少5%的情况下,该算法的正确点数增加了30%以上,单点平均耗时减少50%以上。

LATCH母乳喂养评估表在产妇住院期纯母乳喂养实践中的应用

目的探究LATCH母乳喂养评估表在提高产妇住院期纯母乳喂养率的效果。方法选择2019年5月—2019年11月在本院产科分娩且母婴同室的400例产妇作为研究对象,根据随机数字表法分为对照组200例和观察组200例,对照组采用常规的母乳喂养指导方法进行指导,观察组在常规母乳喂养指导前应用LATCH母乳喂养评估表进行评估,根据评估结果进行个性化的母乳喂养指导,比较两组产妇在住院期间的纯母乳喂养率、乳头皲裂发生率、对护理工作的满意度。结果观察组产妇住院期间纯母乳喂养率明显高于对照组,差异有统计学意义(P<0.01);观察组产妇乳头皲裂发生率明显低于对照组,差异有统计学意义(P<0.05);两组产妇对护理工作满意度有统计学意义(P<0.05)。结论应用LATCH母乳喂养评表可以降低产妇乳头皲裂发生率,提高产妇住院期纯母乳喂养率以及产妇对护理工作满意度。

12Gb/s 0.25μm CMOS Low-Power 1∶4 Demultiplexer

A low power 12Gb/s single-stage 1 ： 4 demultiplexer （DEMUX） applied in SONET OC-192 is realized in TSMC＇s mix-signal 0. 25μm CMOS. All of the circuits are in source coupled FET logic （SCFL） to achieve as high a speed as possible and suppress common mode distortions. This DEMUX is featured for achieving singlestage demultiplexing by using a quarter-rate IQ clock. This method not only reduces the components of the DEMUX but also lowers its power dissipation. The fabricated DEMUX operates error free at 12Gb/s by 231 - 1 pseudorandom bit sequences in on-wafer testing. The chip size is 0. 9mm × 0.9mm and the power dissipation is only 210mW with a single 2.5V supply.

10 Gbit/s 0.25μm CMOS 1∶4 demultiplexer

A 10 Gbit/s (STM-64, OC-192) 1:4 demultiplexer (DEMUX) with 4-phase clock wasachieved in TSMC's standard 0.25 μm complementary metal-oxide-semiconductor (CMOS) technique. Allof the circuits are in source coupled FET logic (SCFL) to achieve as high as possible speed andsuppress common mode distortions. This DEMUX is featured by constant-delay buffers to generate a4-phase clock and adjust skews of the four channel outputs. The fabricated DEMUX operates error freeat 10 Gbit/s by 2^(31) -1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rootmean square (rms) jitter, rising and failing edge of the eye-diagram are 11, 123 and 137 ps,respectively. The chip size is 0.9 mm x 1.2 mm and the power dissipation is 550 mW with a 3. 3 Vsupply.