Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

Low Gate Voltage Operated Multi-emitter-dot H^+ Ion-Sensitive Gated Lateral Bipolar Junction Transistor

A low gate voltage operated multi-emitter-dot gated lateral bipolar junction transistor （BJT） ion sensor is proposed. The proposed device is composed of an arrayed gated lateral BJT, which is driven in the metal-oxidesemiconductor field-effect transistor （MOSFET）-BJT hybrid operation mode. Further, it has multiple emitter dots linked to each other in parallel to improve ionic sensitivity. Using hydrogen ionic solutions as reference solutions, we conduct experiments in which we compare the sensitivity and threshold voltage of the multi-emitter-dot gated lateral BJT with that of the single-emitter-dot gated lateral BJT. The multi-emitter-dot gated lateral BJT not only shows increased sensitivity but, more importantly, the proposed device can be operated under very low gate voltage, whereas the conventional ion-sensitive field-effect transistors cannot. This special characteristic is significant for low power devices and for function devices in which the provision of a gate voltage is difficult.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.

A novel 4H-SiC lateral bipolar junction transistor structure with high voltage and high current gain

In this paper, a novel structure of a 4H-SiC lateral bipolar junction transistor （LBJT） with a base tield plate and double RESURF in the drift region is presented. Collector-base junction depletion extension in the base region is restricted by the base field plate. Thin base as well as low base doping of the LBJT therefore can be achieved under the condition of avalanche breakdown. Simulation results show that thin base of 0.32 μm and base doping of 3 × 1017 cm 3 are obtained, and corresponding current gain is as high as 247 with avalanche breakdown voltage of 3309 V when the drift region length is 30 μm. Besides, an investigation of a 4H-SiC vertical BJT （VBJT） with comparable breakdown voltage （3357 V） shows that the minimum base width of 0.25 ~tm and base doping as high as 8 × 10^17 cm^-3 contribute to a maximum current gain of only 128.

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored （CS） layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the cartier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop （Von）. In the off-state, due to the uniform carder distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss （Eoff）. Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.

A snapback-free TOL-RC-LIGBT with vertical P-collector and N-buffer design

A reverse-conducting lateral insulated-gate bipolar transistor （NI.2-LltJlS｜） with a trench oxide layer （IUL）, teaturlng a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surface and bulk electric fields of the N-drift region, thus the breakdown voltage （BV） is improved. Secondly, the vertical N-buffer layer increases the voltage drop VpN of the P-collector/N-buffer junction, thus the snapback is suppressed. Thirdly, the P-body and the vertical N-buffer act as the anode and the cathode, respectively, to conduct the reverse current, thus the inner diode is integrated. As shown by the simulation results, the proposed RC-LIGBT exhibits trapezoidal electric field distribution with BV of 342.4 V, which is increased by nearly 340% compared to the conventional RC-LIGBT with triangular electric fields of 100.2 V. Moreover, the snapback is eliminated by the vertical N-buffer layer design, thus the reliability of the device is improved.

Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor(LIGBT)based on silicon-on-insulator(SOI)structure is proposed and investigated.This device features a compound dielectric buried layer(CDBL)and an assistant-depletion trench(ADT).The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that,under the same breakdown voltage(BV)condition,allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers.Reducing their numbers helps in fast-switching.Furthermore,the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel.The simulation results show that the BV of the proposed LIGBT is increased by 113%compared with the conventional SOI LIGBT of the same length L_(D).Contrastingly,the length of the drift region of the proposed device(11.2μm)is about one third that of a traditional device(33μm)with the same BV of 141 V.Therefore,the turn-off loss(E_(OFF))of the CDBL SOI LIGBT is decreased by 88.7%compared with a conventional SOI LIGBT when the forward voltage drop(VF)is 1.64 V.Moreover,the short-circuit failure time of the proposed device is 45%longer than that of the conventional SOI LIGBT.Therefor,the proposed CDBL SOI LIGBT exhibits a better V_(F)-E_(OFF)tradeoff and an improved short-circuit robustness.