Analysis of hot-carrier degradation in N-LDMOS transistor with step gate oxide

In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.

Thermal fronts and cross-frontal heat flux in the southern Huanghai Sea and the East China Sea

Synoptic features in/around thermal fronts and cross-frontal heat fluxes in the southern Huanghai./Yellow Sea and East China Sea （HES） were examined using the data collected from four airborne expendable bathythermograph surveys with horizontal approxmately 35 km and vertical 1 m（from the surface to 400 m deep） spacings. Since the fronts are strongly affected by HES current system, the synoptic thermal features in/around them represent the interaction of currents with surrounding water masses. These features can not be obtained from climatological data. The identified thermal features are listed as follows ： （ 1 ） multiple boundaries of cold water, asymmetric thermocline intrusion, locally-split front by homogeneous water of approxmately 18 ℃, and mergence of the front by the Taiwan Warm Current in/around summertime southern Cheju - Changjiang/Yangtze front and Tsushima front; （2） springtime frontal eddy-like feature around Tsushima front; （3） year-round cyclonic meandering and summertime temperature-inversion at the bottom of the surface mixed layer in Cheju - Tsushima front; and （4） multistructure of Kuroshio front. In the Kuroshio front the mean variance of vertical temperature gradient is an order of degree smaller than that in other HES fronts. The southern Cheju- Changjiang front and Cheju -Tsushima front are connected with each other in the summer with comparable cross-frontal temperature gradient. However, cross-frontal heat flux and lateral eddy diffusivity are stronger in the southern Cheju - Changjiang front. The cross-frontal heat exchange is the largest in the mixing zone between the modified Huanghai Sea bottom cold water and the Tsushima Warm Current, which is attributable to enhanced thermocline intrusions.

Lead zirconate titanate behaviors in an LDMOS

The behaviors of lead zirconate titanate （PZT） deposited as the dielectric for high-voltage devices are investigated experimentally and theoretically. The devices demonstrate not only high breakdown voltages above 350 V, but also excellent memory behaviors. A drain current–gate voltage （ID-VG） memory window of about 2.2 V is obtained at the sweep voltages of ±10 V for the 350-V laterally diffused metal oxide semiconductor （LDMOS）. The retention time of about 270 s is recorded for the LDMOS through a controlled ID-VG measurement. The LDMOS with memory behaviors has potential to be applied in future power conversion circuits to boost the performance of the energy conversion system.

A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices

A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure,only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources.It completely considers the following effects：non-linear conductivity,geometry dependence of sensitivity,temperature drift,lateral diffusion,and junction field effect.The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator.The simulation results are in good accordance with the classic experimental results reported in the literature.

Experimental investigation on flow characteristics of a transverse jet with an upstream vortex generator

This paper aims at probing the flow characteristics of a jet in supersonic crossflow(JISC)by installing a vortex generator(VG)upstream of the jet orifice.Nanoparticle planar laser scattering(NPLS)and stereo-particle image velocimetry(SPIV)technologies were employed to observe the flowfield,and three cases were designed for comparison.CASE0 stands for JISC without passive VG.In CASE1 and CASE2,VG is installed at 20 mm and 80 mm upstream away from the jet orifice,respectively.Transient flow structures show that two flow modes exist when the VG wake interacts with the JISC.In CASE1,vortices are induced from both sides of the jet plume because of the VG wake.This leads to a complex streamwise vortex system.Penetration and lateral diffusion are enhanced.In CASE2,intermittent large-scale eddies in the VG wake cause large streamwise vortices at the windward side of the jet.The penetration depth is also enhanced while the lateral diffusion is restrained.In addition,experimental results show that the penetration depth is approximately 8.5%higher in CASE1 than that in CASE0,and the lateral diffusion is larger by about 17.0%.In CASE2,the penetration is increased by about 26.2%,while the lateral diffusion is enhanced by just 0.5%.

Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection

The trigger voltage walkin effect has been investigated by designing two different laterally diffused metal-oxide-semiconductor （LDMOS） transistors with an embedded silicon controlled rectifier （SCR）. By inserting a P＋ implant region along the outer and the inner boundary of the N＋ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5/zm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse （TLP） and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

ESD protection design for the gate oxide of an RF-LDMOS

This paper presents the investigation of integrated electrostatic discharge （ESD） protection design for the gate oxide of an RFLDMOS （radio frequency lateral double diffusion MOS）. Through a comprehensive dis cussion of experimental and simulated results, a cascoded NMOS is presented as appropriate integrated gate oxide ESD protection with a high holding voltage and a flexible ESD design window.