Objective This study focused on the Namco, the largest lake on the Tibet plateau as well as the highest large lake in the world. A large imbalance between water input and output of this lake has attracted great atten...Objective This study focused on the Namco, the largest lake on the Tibet plateau as well as the highest large lake in the world. A large imbalance between water input and output of this lake has attracted great attention in the field of hydrogeology during recent years. As there is no surface outflow from Namco, the large water imbalance can only be explained by water seepage. Synthetic aperture radar （SAR） image data were used for the first time in combination with hydrological data actually measured in the field and meteorological station data, to quantitatively acquire the information of surface fluctuation, water storage variation, and to estimate groundwater leakage from Namco Lake. The results provide theoretical support and data for further understanding the processes and extent of water resource response to global climate change, and also provide a scientific basis for rational development and utilization of water resource in the Tibetan Plateau.展开更多
Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (...Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (BTBT) leakages are considered three maindeterminants of total leakage current. Up to now, how to accurately estimate leakage current oflarge-scale circuits within endurable time remains unsolved, even though accurate leakage modelshave been widely discussed. In this paper, the authors first dip into the stack effect of CMOStechnology and propose a new simple gate-level leakage current model. Then, a table-lookup basedtotal leakage current simulator is built up according to the model. To validate the simulator,accurate leakage current is simulated at circuit level using popular simulator HSPICE forcomparison. Some further studies such as maximum leakage current estimation, minimum leakage currentgeneration and a high-level average leakage current macromodel are introduced in detail.Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage currentestimation methods are very accurate and efficient.展开更多
基金financially supported by the National Natural Science Foundation of China(grant No.61301025)the Jiangsu Provincial Natural Science Foundation of China(grant No.BK20130853)the Fundamental Research Funds for the Central Universities(grant No.2016B07114)
文摘Objective This study focused on the Namco, the largest lake on the Tibet plateau as well as the highest large lake in the world. A large imbalance between water input and output of this lake has attracted great attention in the field of hydrogeology during recent years. As there is no surface outflow from Namco, the large water imbalance can only be explained by water seepage. Synthetic aperture radar （SAR） image data were used for the first time in combination with hydrological data actually measured in the field and meteorological station data, to quantitatively acquire the information of surface fluctuation, water storage variation, and to estimate groundwater leakage from Namco Lake. The results provide theoretical support and data for further understanding the processes and extent of water resource response to global climate change, and also provide a scientific basis for rational development and utilization of water resource in the Tibetan Plateau.
文摘Leakage current of CMOS circuit increases dramatically with the technologyscaling down and has become a critical issue of high performance system. Subthreshold, gate andreverse biased junction band-to-band tunneling (BTBT) leakages are considered three maindeterminants of total leakage current. Up to now, how to accurately estimate leakage current oflarge-scale circuits within endurable time remains unsolved, even though accurate leakage modelshave been widely discussed. In this paper, the authors first dip into the stack effect of CMOStechnology and propose a new simple gate-level leakage current model. Then, a table-lookup basedtotal leakage current simulator is built up according to the model. To validate the simulator,accurate leakage current is simulated at circuit level using popular simulator HSPICE forcomparison. Some further studies such as maximum leakage current estimation, minimum leakage currentgeneration and a high-level average leakage current macromodel are introduced in detail.Experiments on ISCAS85 and ISCAS89 benchmarks demonstrate that the two proposed leakage currentestimation methods are very accurate and efficient.
