To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorith...To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorithm for combinatorial hardware Trojans. Based on the greedy algorithm and the recursive construction method in the combination test,the method formulates appropriate and useful greedy strategy and generates test vector sets with different combinatorial correlation coefficients to activate hardware Trojans in target circuits. The experiment was carried out based on advanced encryption standard（ AES） hardware encryption circuit,different combinatorial hardware Trojans were implanted in AES as target circuits,the experiment of detecting hardware Trojans in target circuits was performed by applying the proposed method and different combinatorial hardware Trojans in target circuits were activated successfully many times in the experiment. The experimental results showthat the test vector sets generated using the proposed method could effectively activate combinatorial hardware Trojans,improve the probability of the hardware Trojan being activated,and also be applied to practice.展开更多
In this paper, we present a detection technique of and-parallelism in logic programs. The detection consists of three phases: analysis of entry modes, derivation of exit modes and determination of execution graph expr...In this paper, we present a detection technique of and-parallelism in logic programs. The detection consists of three phases: analysis of entry modes, derivation of exit modes and determination of execution graph expressions. Compared with other techniques, our approach, with the compile-time program-level data-dependence analysis of logic programs, can efficiently exploit and-parallelism in logic programs. Two precompilers, based on our technique and DeGroot' s approach respectively, have been implemented in SES-PIM system. Through compiling and running some typical benchmarks in SES-PIM, we conclude that our technique can, in most cases, exploit as much and-parallelism as the dynamic approach does under 'producer-consumer' scheme, and needs less dynamic overhead while exploiting more and- parallelism than DeGroot's approach does.展开更多
文摘To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorithm for combinatorial hardware Trojans. Based on the greedy algorithm and the recursive construction method in the combination test,the method formulates appropriate and useful greedy strategy and generates test vector sets with different combinatorial correlation coefficients to activate hardware Trojans in target circuits. The experiment was carried out based on advanced encryption standard（ AES） hardware encryption circuit,different combinatorial hardware Trojans were implanted in AES as target circuits,the experiment of detecting hardware Trojans in target circuits was performed by applying the proposed method and different combinatorial hardware Trojans in target circuits were activated successfully many times in the experiment. The experimental results showthat the test vector sets generated using the proposed method could effectively activate combinatorial hardware Trojans,improve the probability of the hardware Trojan being activated,and also be applied to practice.
基金This research was partially supported by the Fok Ying Tung Education Foundation
文摘In this paper, we present a detection technique of and-parallelism in logic programs. The detection consists of three phases: analysis of entry modes, derivation of exit modes and determination of execution graph expressions. Compared with other techniques, our approach, with the compile-time program-level data-dependence analysis of logic programs, can efficiently exploit and-parallelism in logic programs. Two precompilers, based on our technique and DeGroot' s approach respectively, have been implemented in SES-PIM system. Through compiling and running some typical benchmarks in SES-PIM, we conclude that our technique can, in most cases, exploit as much and-parallelism as the dynamic approach does under 'producer-consumer' scheme, and needs less dynamic overhead while exploiting more and- parallelism than DeGroot's approach does.
