An Energy-Efficient 12b 2.56 MS/s SAR ADC Using Successive Scaling of Reference Voltages

This paper presents an energy efficient architecture for successive approximation register(SAR)analog to digital converter(ADC).SAR ADCs with a capacitor array structure have been widely used because of its simple architecture and relatively high speed.However,conventional SAR ADCs consume relatively high energy due to the large number of capacitors used in the capacitor array and their sizes scaled up along with the number of bits.The proposed architecture reduces the energy consumption as well as the capacitor size by employing a new array architecture that scales down the reference voltages instead of scaling up the capacitor sizes.The proposed 12-bit SAR ADC is implemented in Complementary Metal Oxide Semiconductor(CMOS)0.13 um library using Cadence Virtuoso design tool.Simulation results and mathematical model demonstrate the overall energy savings of up to 97.3%compared with conventional SAR ADC,67%compared with the SAR ADC with split capacitor,and 35%compared with the resistor and capacitor(R&C)Hybrid SAR ADC.The ADC achieves an effective number of bits(ENOB)of 11.27 bits and consumes 61.7 uW at sampling rate of 2.56 MS/s,offering an energy consumption of 9.8 fJ per conversion step.The proposed SAR ADC offers 95.5%reduction in chip core area compared to conventional architecture,while occupying an active area of 0.088 mm2.

High voltage generator circuit with low power and high efficiency applied in EEPROM

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory（EEPROM）.The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage（V_（th）） MOSFET and the charge transfer switch（CTS） charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48μW and a higher pumping efficiency（83.3%） than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.

Design and implementation of an ultra-low power passive UHF RFID tag

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18μm CMOS process with a die size of 800×800μm;. Measurement results show that the total power consumption of the tag chip is only 7.4μW with a sensitivity of -12 dBm.

A low power CMOS VCO using inductive-biasing with high performance FoM

A novel voltage-controlled oscillator（VCO） topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using timevarying phase noise theory derives closed-form symbolic formulas for the 1/f^2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 m CMOS technology. Working under a 0.3 V supply voltage with 1.2 m W power consumption, the measured phase noise of the VCO is –119.4 d Bc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an Fo M of 192.5 d Bc/Hz.

A 1.2-V,84-dB∑△ADM in 0.18-μm digital CMOS technology

A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.