Design and performance of a high-speed and low-noise preamplifier for SiPM

Considering the R&D for upgrading the K^(0)_(L) andμdetectors in the Belle II experiment using a scintillator and silicon pho-tomultiplier(SiPM),we designed a compact high-speed and low-noise preamplifier.The preamplifier demonstrated a good gain stability,bandwidth of 426 MHz,baseline noise level ofσ≈0.6 mV,dynamic range of up to170 mV of the input signal amplitude,good time resolution of 20 ps,and it can be comprehensively applied to SiPMs.Adopting pole-zero-cancelation in the preamplifier reduces both the rise and fall times of the SiPM signal,which can significantly improve the time resolution and reduce the pile-up when using a large SiPM or an array of SiPMs.Various combinations of the preamplifier and several types of SiPMs demonstrated time resolutions better than 50 ps for most cases;when the number of detected photons was larger than 60,a time resolution of approximately 25 ps was achieved.

Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

OPTIMIZATION DESIGN METHOD FOR INPUT IMPEDANCE MATCHING NETWORK OF LOW NOISE AMPLIFIER

According to the theories of optimal noise match and optimal power match, a method for calculating the optimal source impedance of low noise amplifier （LNA） is proposed based on the input reflection coefficient S11. Moreover.with the help of Smith chart, the calculation process is detailed, and the trade-off between the lowest noise figure and the maximum power gain is obtained during the design of LNA input impedance matching network. Based on the Chart 0. 35-μm CMOS process, a traditional cascode LNA circuit is designed and manufactured. Simulation and experimental results have a good agreement with the theoretical analysis, thus proving the correctness of theoretical analysis and the feasibility of the method.

Design and analysis on four stage SiGe HBT low noise amplifier

Focusing on the linearity shortcoming on a bipolar low noise amplifier(LNA),a new 6 ~14GHz four stage SiGe HBT LNA is proposed.This amplifier adopts a method of gain allocation on multiple stages to avoid the limitation on linearity especially with the addition of negative gain on the third stage.To realize gain flatness,extra zero is introduced to compensate the gain roll-off formed by pole,and local shunt-shunt negative feedback is used to widen the bandwidth as well as optimize circuit' s noise.Simulated results have shown that in 6 ~14GHz,this circuit achieves noise figure(NF) less than 3dB,gain of 17.8dB(+0.2dB),input and output reflection parameters of less than- 10 dB,and the K factor is above 1.15.

Analysis, Design and Implementation of SiGe Wideband Dual-Feedback Low Noise Amplifier

A wideband dual-feedback low noise amplifier （LNA） was analyzed, designed and implemented using SiGe heterojunction bipolar transistor （HBT） technology. The design analysis in terms of gain, input and output matching, noise and poles for the amplifier was presented in detail. The area of the complete chip die, including bonding pads and seal ring, was 655 μm × 495 μm. The on-wafer measurements on the fabricated wideband LNA sample demonstrated good performance： a small-signal power gain of 33 dB with 3-dB bandwidth at 3.3 GHz was achieved; the input and output return losses were better than - 10 dB from 100 MHz to 4 GHz and to 6 GHz, respectively; the noise figure was lower than 4.25 dB from 100 MHz to 6 GHz; with a 5 V supply, the values of OPtdB and OIP3 were 1.7 dBm and 11 dBm at 3-dB bandwidth, respectively.

Design of 5GHz low noise amplifier with HBM SiGe 0. 13μm BiCMOS process

A fully integrated low noise amplifier( LNA) for WLAN 802. 11 ac is presented in this article.A cascode topology combining BJT and MOS transistor is used for better performance. An inductive source degeneration is chosen to get 50 Ohm impedance matching at the input. The noise contribution of common gate transistor is analyzed for the first time. The designed LNA is verified with IBM silicon-germanium(SiGe ) 0. 13μm BiCMOS process. The measured results show that the designed LNA has the gain of 13 dB and NF of 2. 8 dB at the center frequency of 5. 5 GHz. The input reflection S11 and output reflection S22 are equal to-19 dB and-11 dB respectively. The P-1 dB and IIP3 are-8. 9 dBm and 6. 6 dBm for the linearity performance respectively. The power consumption is only 1. 3 mW under the 1. 2 V supply. LNA achieves high gain,low noise,and high linearity performance,allowing it to be used for the WLAN 802. 11 ac applications.

A wideband CMOS variable gain low noise amplifier

In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.

Implementation and noise optimization of a 433 MHz low power CMOS LNA

A low power 433 MHz CMOS （complementary metal- oxide-semiconductor transistor） low noise amplifier（LNA）, used for an ISM （ industrial-scientific-medical ） receiver, is implemented in a 0. 18 μm SMIC mixed-signal and RF （ radio frequency） CMOS process. The optimal noise performance of the CMOS LNA is achieved by adjusting the source degeneration inductance and by inserting an appropriate capacitance in parallel with the input transistor of the LNA. The measured results show that at 431 MHz the LNA has a noise figure of 2.4 dB. The S21 is equal to 16 dB, S11 = -11 dB, S22 = -9 dB, and the inverse isolation is 35 dB. The measured input 1-dB compression point （PtdB） and input third-order intermodulation product （IIP3）are - 13 dBm and -3 dBm, respectively. The chip area is 0. 55 mm × 1.2 mm and the DC power consumption is only 4 mW under a 1.8 V voltage supply.

Design of Low-Voltage Low Noise Amplifiers with High Linearity

A CMOS radio frequency low noise amplifier with high linearity and low operation voltage of less than 1.0V is presented.In this circuit,an auxiliary MOSFET in the triode region is used to boost the linearity.Simulation shows that this method can boost the input-referred 3rd-order intercept point with much less power dissipation than that of traditional power/linearity tradeoff solution which pays at least 1dB power for 1dB linearity improvement.It is also shown that the size of the common-gate PMOS transistor needs to be optimized to reduce its loaded input impedance so as not to degrade the linearity due to high voltage gain at its source terminal.The simulation is carried out with TSMC 0.18μm RF CMOS technology and SpectreRF.

Optimum Design for a Low Noise Amplifier in S-Band

An optimum design of a low noise amplifier （LNA） in S-band working at 2-4 GHz is described. Choosing FHC40LG high electronic mobility transistor （HEMT）, the noise figure of the designed amplifier simulated by Microwave Office is no more than 1.5 dB, meanwhile the gain is no less than 20 dB in the given bandwidth. The simulated results agree with the performance of the transistor itself well in consideration of its own minimum noise figure （0.3 dB） and associated gain （15.5 dB）. Simultaneously, the stability factor of the designed amplifier is no less than 1 in the given bandwidth.

Research on the Effect of High Power Microwave on Low Noise Amplifier and Limiter Based on the Injection Method

The reliability of electronic device is threatened in high power microwave (HPM) environment. In accordance with the situation that the emulation is ineffective in evaluating the accuracy and precision of the HPM effect to electronic device, the experimental method is used to resolve the problem. Low Noise Amplifier (LNA) and Limiter are selected as the objects for the experiments, the structural characteristic of the front-end of radar receiver is described, the phenomena and criterion are elaborated and analyzed using injection method due to its ability to get an accurate threshold avoiding the complex coupling, the basic principle of injection experiment is demonstrated, and the method and process of effect experiment about Low Noise Amplifier and Limiter are also explained. The experimental system is established, and the system is composed of low power microwave source such as TWT, test equipment for obtaining the effect parameters, and some of auxiliary equipments as camera, optical microscope or electron microscopy, attenuator, detector, and directional coupler etc. The microwave delivered from source is adjusted to the power infused by attenuator, and pour in the decanting point of effecter via directional coupler, then the couple signal created by directional coupler is input to the recording instrument after detecting by detector, finally the power of effecter is obtained. The value of power, which damages the effecter in the microwave pulse environment, is classified at the index of sensitivity, and the threshold is obtained by power diagnose and wave test. Some regular understandings of the HPM effect to electronic device are obtained based on the results of the experiments. It turns out that the index of electronic device is influenced significantly by the energy via front door coupling, the MOSFET made up of GaAs is the most wearing part to HPM in LNA, the damage threshold of LNA is about 40dBm under single pulse while in repetitive pulse the value is from 33.3dBm to 43.9dBm according to different wave band. The damage threshold of Limiter is about 56dBm to80dBm.

DESIGN AND ANALYSIS OF INTEGRATED OPERATIONAL AMPLIFIER XD1531 WITH LOW NOISE AT LOW FREQUENCIES

Principles of design are described for the low frequency integrated operationalamplifler XD1531 with low noise. The procedures of design of both the circuit structure and the tran-sistor shape are considered. The first stage of the circuit is designed with the methods of low noise atlow frequencies. The measures which decrease noises, especially, the 1/f noise originating .from thesemiconductor surface state and defects, are used for the transistor structure design. With analysisand comparison to products here and abroad in characteristics, it is shown that XD1531 has a lowernoise index at low frequencies than others, and the effectiveness of design methods for bringing lownoises have been demonstrated.

3 - 10 GHz Ultra-Wideband Low-Noise Amplifier Using Inductive-Series Peaking Technique with Cascode Common-Source Circuit

The objective of this paper is to investigate a ultra-wideband (UWB) low noise amplifier (LNA) by utilizing a two-stage cascade circuit schematic associated with inductive-series peaking technique, which can improve the bandwidth in the 3-10 GHz microwave monolithic integrated circuit (MMIC). The proposed UWB LNA amplifier was implemented with both co-planer waveguide (CPW) layout and 0.15-μm GaAs D-mode pHEMT technology. Based on those technologies, this proposed UWB LNA with a chip size of 1.5 mm x 1.4 mm, obtained a flatness gain 3-dB bandwidth of 4 - 8 GHz, the constant gain of 4 dB, noise figure lower than 5 dB, and the return loss better than –8.5 dB. Based on our experimental results, the low noise amplifier using the inductive-series peaking technique can obtain a wider bandwidth, low power consumption and high flatness of gain in the 3 - 10 GHz. Finally, the overall LNA characterization exhibits ultra-wide bandwidth and low noise characterization, which illustrates that the proposed UWB LNA has a compact size and favorable RF characteristics. This UWB LNA circuit demonstrated the high RF characterization and could provide for the low noise micro-wave circuit applications.

A 400 MHz Low Noise Amplifier at Cryogenic Temperature for Superconductor Filter System

A cryogenic low noise amplifier （LNA） using Agilent high electron mobility transistor （HEMT） for 380 MHzto 480 MHz is designed and fabricated, and the excellent cryogenic performance in superconducting receiver front-end for communication system is achieved. A special input impedance matching topology is implemented to provide low noise figure （NF） and good input matching in this cryogenic LNA design. The measurement results show that the NF is within 0.25 dB from the minimum NF of a single transistor, the power gain is above 20 dB, the flatness is within 1 dB, and the maximum input return loss is lower than -20 dB in bandwidth.

Inductorless CMOS Low Noise Amplifier for Multiband Application in 0.1–1.2 GHz

A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.

A NOVEL Ku-BAND LOW NOISE AMPLIFIER WITH HEMT AND GaAs MMIC

A novel Ku-band low noise amplifier with a high electron mobility transistor (HEMT)and a GaAs monolithic microwave integrated circuit (MMIC) has been demonstrated. Its noisefigure is less-than 1.9dB with an associated gain larger than 27dB and an input/output VSWRless than 1.4 in the frequency range of 11.7-12.2GHz. The HEMT and the microwave series in-ductance feedback technique are used in the first stage of the amplifier, and a Ku-band MMIC isemployed in the last stage. The key to this design is to achieve an optimum noise match and a min-imum input VSWR matching simultaneously by using the microwave series inductance feedbackmethod. The B J-120 waveguides are used in both input and output of the amplifier.

A 9 - 10.6 GHz Microstrip Antenna—UWB Low Noise Amplifier with Differential Noise Canceling Technique for IoT Applications

An ultra-wide band (UWB) receiver front-end that operates at the UWB frequency range, starting from 9 GHz - 10.6 GHz is proposed in this paper. The proposed system consists of an off-chip microstrip antenna and CMOS differential low noise amplifier with a differential noise canceling (DNC) technique. The proposed antenna is trapezoidal dipole shaped with balun and printed on a low-cost FR4 substrate with dimensions 10 × 10 × 0.8 mm3. The balun circuit integrated with the ground antenna to improve the antenna impedance matching. Noise canceling is obtained by using a differential block with each stage having 2 amplifiers that generate differential signals, subtracted to improve total noise performance. The proposed DNC block improves NF by 50% while increasing total power consumption with only 0.1 Mw. The differential CMOS cascode LNA with DNC block is implemented using UMC 0.13 μm CMOS process, exhibits a flat gain of 19 dB, maximum noise figure of 2.75 dB, 1 dB compression point −16 dBm and 3rd order intercept point (IIP3) −10 dBm. The proposed system has total DC power consumption of 2.8 mW at 1.2 V power supply.

An X-Band Low Noise Amplifier Design for Marine Navigation Radars

In this paper, the design of a 9.1 GHz Low Noise Amplifier (LNA) of a RADAR receiver that is used in the Navy is presented. For the design of the LNA, we used GaAs Field-Effect Transistors (FETs) from Agilent ADS component library. In order to keep the cost of the circuit in low prices and the performance high, we design a two-stage LNA.

A compact and reconfigurable low noise amplifier employing combinational active inductors and composite resistors feedback techniques

A compact and reconfigurable low noise amplifier(LNA)is proposed by combining an input transistor,composite transistors with Darlington configuration as the amplification and output transistor,T-type structure composite resistors instead of a simplex structure resistor,a shunt inductor feedback realized by a tunable active inductor(AI),a shunt inductor peaking technique realized by another tunable AI.The division and collaboration among different resistances in the T-type structure composite resistor realize simultaneously input impedance matching,output impedance matching and good noise performance;the shunt feedback and peaking technique using two tunable AIs not only extend frequency bandwidth and improve gain flatness,but also make the gain and frequency band can be tuned simultaneously by the external bias of tunable AIs;the Darlington configuration of composite transistors provides high gain;furthermore,the adoption of the small size AIs instead of large size passive spiral inductor,and the use of composite resistors make the LNA have a small size.The LNA is fabricated and verified by GaAs/InGaP hetero-junction bipolar transistor(HBT)process.The results show that at the frequency of 7 GHz,the gain S_(21)is maximum and up to 19 dB;the S_(21)can be tuned from 17 dB to 19 dB by tuning external bias of tunable AIs,that is,the tunable amount of S_(21)is 2 dB,and similarly at 8 GHz;the tunable range of 3 dB bandwidth is 1 GHz.In addition,the gain S_(21)flatness is better than 0.4 dB under frequency from 3.1 GHz to 10.6 GHz;the size of the LNA only has 760μm×1260μm(including PADs).Therefore,the proposed strategies in the paper provide a new solution to the design of small size and reconfigurable ultra-wideband(UWB)LNA and can be used further to adjust the variations of gain and bandwidth of radio frequency integrated circuits(RFICs)due to package,parasitic and the variation of fabrication process and temperature.