A hybrid storage technology for low power consumption and high I/O performance in an IPTV set-top box

A new method of prefetching data blocks from the NVCache to the page cache in main memory and cascading prefetching n-blocks from a hard disk to the NVCache together was proposed to reduce the spin-up frequency of a hybrid hard disk drive and thus enhance I/O performance.The proposed method consists of three steps:1) Analyzing the pattern of read requests in block units;2) Determining the number of blocks prefetched to the NVCache;3) Replacing blocks in the NVCache according to the block replacement policy.The proposed method can reduce the latency time of a hybrid hard disk and optimize the power consumption of an IPTV set-top box.Experimental results show that the proposed method provides better average response time compared to an existing adaptive multistream prefetching(AMP) method by 25.17%.It also reduces by 20.83% the average power consumption over that of the existing external caching in energy saving storage system(EXCES) method.

Analysis and Research on Low-Cost and Non-Intrusive Power Metering Chip

Metering technology is one of the core technologies of the smart power grid. The overall metering solution and related products have a wide market space in the whole process of power production, which bring new opportunities for power distribution development from automation to intelligentialize, and provide technical supports for the power metering system platform. Because of the importance of metering products and their market demand, this paper focuses on the design of a simple power metering chip with low-cost, low-precision and non-invasive, so as to lay the foundation for the development and practical technology accumulation of power metering products. The design achieves low cost by reducing the acquisition accuracy, simplifying the collection and sampling methods. This paper studies the chip accuracy, sampling methods, collection methods, and the inference of the chip characteristics requirements.

Low power consumption 4-channel variable optical attenuator array based on planar lightwave circuit technique

The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.

Low Power Consumption Distributed-Feedback Quantum Cascade Lasers Operating in Continuous-Wave Mode above 90℃ at λ～7.2μm

We report on the design and fabrication of λ-7.2μm distributed feedback quantum cascade lasers lot very high temperature cw operation and low electrical power consumption. The cw operation is reported above 90℃. For a 2-mm-long and 10-μm-wide laser coated with high-reflectivity on the rear facet, more than 170mW of output power is obtained at 20℃ with a threshold power consumption of 2.4 W, corresponding to 30mW with a threshold power consumption of 3.9 W at 90℃. Robust single-mode emission with a side-mode suppression ratio above 25 dB is continuously tunable by the heat sink temperature or injection current.

A low-power Rijndael S-Box based on pass transmission gate and composite field arithmetic

Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.

A 2.4-GHz-Low-Power CMOS RF Transmitter for IEEE 802.15.4 Standard

This paper presents the experimental results of a low-power RF transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology. In order to make an adaptive RF transmitter, several factors must be considered. The most important factors are performances, power consumption, output power, noise factor, and cost. The RF transmitter comprises a quadrature passive mixer, and a power amplifier. The proposed RF transmitter consumes only 10.8-mW under a supply voltage of 1.8-V.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

Low-noise,low-power-consumption seafloor vector magnetometer

The seafloor vector magnetometer is an effective tool for marine geomagnetic surveys and seafloor magnetotelluric(MT)detection.However,the noise,power consumption,cost,and volume characteristics of existing seafloor vector magnetometers are insufficient for practical use.Therefore,a low-noise,low-power-consumption seafloor vector magnetometer that can be used for data acquisition of deep-ocean geomagnetic vector components is developed and presented.A seafloor vector magnetometer mainly consists of a fluxgate sensor,data acquisition module,acoustic release module,glass sphere,frame,burn-wire release,and anchor.A new low-noise data acquisition module and a fluxgate sensor greatly reduce power consumption.Furthermore,compact size is achieved by integrating an acoustic telemetry module and replacing the acoustic release with an external burn-wire release.The new design and magnetometer characteristics reduce the volume of the instrument and the cost of hardware considerably,thereby improving the integrity and deployment efficiency of the equipment.Theoretically,it can operate for 90 days underwater at a maximum depth of 6000 m.The seafloor vector magnetometer was tested in the South China Sea and the Philippine Sea and obtained high-quality geomagnetic data.The deep-water environment facilitates magnetic field data measurements,and the magnetometer has an approximate noise level of 10 pT/rt(Hz)@1 Hz,a peak-to-peak value error of 0.2 nT,and approximate power consumption of 200 mW.The fluxgate sensor can measure the magnetic field in the lower frequency band and realize geomagnetic field measurements over prolonged periods.

Study of a GaAs MESFET Model with Ultra-Low Power Consumption

A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical parameters and the bias condition. The dependence of the RF performance and DC power consumption on physical, material and technological parameters of EFET is also studied. The optimum range of the physical parameters is given which is useful for the design of active device of ultra low power consumption MMIC.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

Resistive switching characteristic and uniformity of low-power HfO_x-based resistive random access memory with the BN insertion layer

In this letter,the Ta/HfO/BN/TiN resistive switching devices are fabricated and they exhibit low power consumption and high uniformity each.The reset current is reduced for the HfO/BN bilayer device compared with that for the Ta/HfO/TiN structure.Furthermore,the reset current decreases with increasing BN thickness.The HfOlayer is a dominating switching layer,while the low-permittivity and high-resistivity BN layer acts as a barrier of electrons injection into TiN electrode.The current conduction mechanism of low resistance state in the HfO/BN bilayer device is space-chargelimited current(SCLC),while it is Ohmic conduction in the HfOdevice.

Low-Power Design of Ethernet Data Transmission

For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array （FPGA）, a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit （IC） design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.

Development and Static Mode Characterization of a New Low-Loss AC Switch Based on Super-gain BJT

This paper deals with an innovative low-loss AC switch, named as TBBS （transistor based bidirectional switch）, based on the association of super-gain BJTs developed by the GREMAN laboratory. The main characterization results of the super-gain BJT are reminded to identify the key parameters that are essential to build the TBBS. A complete characterization database in static mode of this new AC switch is discussed. In particular, its forward and reverse-biased features have been measured to see the evolution of the DC current gain as a function of the current density. The TBBS makes sense when using the super-gain BJT （bipolar junction transistor） in reverse mode. It means that the reverse DC current gain has to be sufficient （at least higher than l compared with the conventional BJT one）. This new AC switch is bidirectional in current and voltage, totally controllable （turn-on and turn-off） and the most attractive solution in terms of on-state power losses. Further, its manufacturing process is as easier as existing device such as triac.

基于NAT64的6LoWPAN边缘路由器设计

针对目前基于6Lo WPAN边缘路由器只适用与IPv6设备互联、网络报文传输复杂繁琐、边缘路由器映射表复杂且开销大等问题,引入IEEE 802.15.4地址概念对6Lo WPAN网络内报文交互方式与数据包格式进行优化,提出一种6Lo WPAN与IPv4协议转换机制和边缘路由器地址映射转换方法,设计出适合在8位单片机上运行的轻量级微系统,最后用Co AP协议来访问节点数据,验证系统,实现6Lo WPAN网络与IPv4,IPv6网络之间的通信。该方法实现了6Lo WPAN与IPv4网络互联通信,保留6Lo WAPN与IPv6网络通信的功能,同时提高了6Lo WPAN内网络的吞吐量,降低边缘路由器维护地址映射表的开销,提高了边缘路由器效率,有效降低6Lo WPAN网络传输数据时的功耗,提高节点生存时间。

基于6LoWPAN的煤层瓦斯压力监测系统设计

针对目前煤层瓦斯压力监测存在测量精度低、数据传输不及时、设备部署不便等问题,设计了一种基于6LoWPAN的煤层瓦斯压力监测系统。该系统测压节点通过多跳方式在6LoWPAN网络中选择最优路径,将实时采集的瓦斯压力数据传输至边界路由器,边界路由器通过工业以太网将数据传至地面服务器,同时地面设备可通过服务器查询指定区域测压节点的实时监测数据。测试结果表明,该系统可实时、准确地监测煤层瓦斯压力,具有较高的数据通信效率和稳定性,且功耗低。

A Study of Efficient Power Consumption Wireless Communication Techniques/ Modules for Internet of Things (IoT) Applications

A study of wireless technologies for IoT applications in terms of power consumption has been presented in this paper. The study focuses on the importance of using low power wireless techniques and modules in IoT applications by introducing a comparative between different low power wireless communication techniques such as ZigBee, Low Power Wi-Fi, 6LowPAN, LPWA and their modules to conserve power and longing the life for the IoT network sensors. The approach of the study is in term of protocol used and the particular module that achieve that protocol. The candidate protocols are classified according to the range of connectivity between sensor nodes. For short ranges connectivity the candidate protocols are ZigBee, 6LoWPAN and low power Wi-Fi. For long connectivity the candidate is LoRaWAN protocol. The results of the study demonstrate that the choice of module for each protocol plays a vital role in battery life due to the difference of power consumption for each module/protocol. So, the evaluation of protocols with each other depends on the module used.

Selection and Design of WSN Node Based on Solar Power in Facility Greenhouse

In this study, the green energy saving of greenhouse sensor node is de- signed to reduce the system power consumption and high efficiency. The green renewable solar energy resources are used as the energy source of nodes; the lowenergy consumed and cost effective MSP430 chip is used as the main control chip of the processor unit; the transmission frequency of the wireless transmission unit is 433 MHz, which has the characteristics of low power consumption, high signal strength, long transmission distance and small signal attenuation during the transmission; the power supply system unit is composed of monocrystalline silicon solar panel and high performance rechargeable lithium ion battery. The selection basis of each unit is clarified in detail, and optimization is performed by hardware circuit and software program to further reduce power consumption. The power consumption of the node is calculated by the experiment, and the charging conditions of the solar panel used in the node is tested. The results show that the system can achieve the setting target through the selection and design.

基于LoRa的智能道钉系统设计

针对传统道钉缺乏感知能力和交互能力差的问题,设计了一种基于LoRa的智能道钉系统,详细介绍了智能道钉和道钉网关的软硬件设计。智能道钉通过周期性采集道路温度信息,实现道路养护提示和冰冻预警,以提高道路安全性。搭建了LoRa网络环境,满足了公路环境广域覆盖、高可靠性、低功耗的网络传输需求。自定义网络通信协议,实现智能道钉与道钉网关之间的数据传输和远程控制。实验结果表明,智能道钉通信距离为500 m,实现了高效稳定的远程控制;太阳能电池供电方案满足道钉长期工作需求;智能道钉发光性能良好,适合夜间指引防护。

一种基于Android系统网络模块功耗的评估和分析

嵌入式移动便携设备由电池供电,而电池容量却受体积和重量的制约,因此嵌入式移动设备的功耗问题成为研究的一个关键问题。分别采用WIFI和GPRS两种接入网络策略,研究手机系统功耗的变化。实验结果表明,小流量模式(10kb/min)下两种策略电池使用时间减少约50%,大流量模式(2Mbit/min)下能量消耗更快,减少约85%;在传输相等的数据量下,WIFI模式比GPRS模式省电。在两台基于Android系统平台的真机上进行了实验,结果表明,研究降低手机移动网络模块的功耗具有十分重要的意义。

NAND Flash在MSP430嵌入式系统中的应用

本文实现了大容量NANDFLASH在MSP430嵌入式系统中的应用,阐述了NANDFLASH的使用方法,重点介绍了硬件电路设计和软件设计,满足了系统微体积、低功耗的要求。