MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This pape...MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips （SoCs） easily. We have built a multi-core system with ABMA to verify this design, In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.展开更多
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.展开更多
基金supported by the IC Special Foundation of Science and Technology Commission of Shanghai Municipality(Grant No.09706201300)the Shanghai Municipal Commission of Economic and Information(Grant No.090344)the Shanghai High-Technology Industrialization of New Energy Vehicles(Grant No.09625029)
文摘MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body＇s control. Advanced peripheral bus （APB） is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips （SoCs） easily. We have built a multi-core system with ABMA to verify this design, In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation,China (Grant No. ZHD200904)
文摘On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.
