该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μ...该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。展开更多
A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical...A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.展开更多
The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulat...The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulator in a time-hopping ultra wide-band （TH-UWB）communication with a carrier frequency of 4 GHz. In the topology of the OOK modulator circuit, there are three parts, an oscillator with an oscillating frequency of 4 GHz, a T-type attenuator constructed by RF CMOS transistors, and an output impedance matching network with a L-type LC structure. The modulator is controlled by a time-hopping pulse position modulation（TH-PPM） signal. The envelope of the modulated signal varies with the amplitude of the controlling signal. Meanwhile, an output matching network is also designed to match a 50 Ω load. In 0. 18 μm RF CMOS technology, a modulator is designed and simulated. The implemented modulator chip has 65 mV of the output amplitude at a 50 fl load from a 1.8 V supply, and the return loss （ S11 ） at the output port is less than - 10 dB. The chip size is 0. 7 mm × 0. 8 mm, and the power consumption is 12. 3 mW.展开更多
An RF bandpass filter with a Q-enhancement active inductor is presented. The design technique for a tunable Q-enhancement CMOS active inductor operating in the wide RF-band is described. Moreover,issues related to noi...An RF bandpass filter with a Q-enhancement active inductor is presented. The design technique for a tunable Q-enhancement CMOS active inductor operating in the wide RF-band is described. Moreover,issues related to noise and stability of the active inductor are explained. The filter was fabricated in 0.18μm CMOS technolo- gy,and the circuit occupied an active area of only 150μm ×200μm. Measurement results show that the filter centered at 2. 44GHz with about 60MHz bandwidth （3dB） is tunable in center frequency from about 2.07 to 2. 44GHz. The ldB compression point is - 15dBm while consuming 10. 8mW of DC power,and a maximum quality factor of 103 is attained at the center frequency of 2.07GHz.展开更多
A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packagi...A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC.展开更多
提出了一种新的RF-CMOS晶体管在片测试结构寄生模型,模型综合考虑了射频/微波条件下RF-MOST器件在片测试结构中的各种寄生效应.模型考虑了PAD-互连金属、互连金属-DUT(device under test)之间的非连续性,对互连金属和基底之间的寄生效...提出了一种新的RF-CMOS晶体管在片测试结构寄生模型,模型综合考虑了射频/微波条件下RF-MOST器件在片测试结构中的各种寄生效应.模型考虑了PAD-互连金属、互连金属-DUT(device under test)之间的非连续性,对互连金属和基底之间的寄生效应单独进行了考虑.通过引入一个新的元件,对PAD结构基底感性损耗进行表征.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的测试结构寄生效应等效电路建模中,高达40GHz测试和仿真数据验证了模型的良好精度.展开更多
There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commerci...There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.展开更多
A new architecture of CMOS low voltage downconve rsion mixer is presented.With 1.452GHz LO input and 1.45GHz RF input,simulation results show that the conversion gain is 15dB,IIP3 is -4.5dBm,NF is 17dB,the maximum tra...A new architecture of CMOS low voltage downconve rsion mixer is presented.With 1.452GHz LO input and 1.45GHz RF input,simulation results show that the conversion gain is 15dB,IIP3 is -4.5dBm,NF is 17dB,the maximum transient power dissipation is 9.3mW,and DC power dissipation is 9.2mW.The mixer’s noise and linearity analyses are also presented.展开更多
文摘该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。
文摘A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.
文摘针对融合射频识别（RFID）的无线温度传感器节点设计的需求,采用0.18μm 1P6M台积电CMOS工艺,设计了一种低功耗集成温度传感器。该温度传感器首先将温度信号转换为电压信号,然后通过经压控振荡器将电压信号转换为受温度控制的频率信号,再通过计数器,将频率信号转换为数字信号。传感器电路利用MOS管工作在亚阈值区,并采用动态阈值技术获得超低功耗。测试结果显示：所设计的温度传感器仅占用0.051 mm2,功耗仅为101 n W,在0~100℃范围内误差为-1.5~1.2℃。
文摘The insertion loss （IL） of a T-type attenuator is theoretically analyzed. A T-type RF （ radio frequency） CMOS （ complementary metal-oxide-semiconductor ） attenuator is designed as an on-off keying（OOK） modulator in a time-hopping ultra wide-band （TH-UWB）communication with a carrier frequency of 4 GHz. In the topology of the OOK modulator circuit, there are three parts, an oscillator with an oscillating frequency of 4 GHz, a T-type attenuator constructed by RF CMOS transistors, and an output impedance matching network with a L-type LC structure. The modulator is controlled by a time-hopping pulse position modulation（TH-PPM） signal. The envelope of the modulated signal varies with the amplitude of the controlling signal. Meanwhile, an output matching network is also designed to match a 50 Ω load. In 0. 18 μm RF CMOS technology, a modulator is designed and simulated. The implemented modulator chip has 65 mV of the output amplitude at a 50 fl load from a 1.8 V supply, and the return loss （ S11 ） at the output port is less than - 10 dB. The chip size is 0. 7 mm × 0. 8 mm, and the power consumption is 12. 3 mW.
文摘An RF bandpass filter with a Q-enhancement active inductor is presented. The design technique for a tunable Q-enhancement CMOS active inductor operating in the wide RF-band is described. Moreover,issues related to noise and stability of the active inductor are explained. The filter was fabricated in 0.18μm CMOS technolo- gy,and the circuit occupied an active area of only 150μm ×200μm. Measurement results show that the filter centered at 2. 44GHz with about 60MHz bandwidth （3dB） is tunable in center frequency from about 2.07 to 2. 44GHz. The ldB compression point is - 15dBm while consuming 10. 8mW of DC power,and a maximum quality factor of 103 is attained at the center frequency of 2.07GHz.
文摘A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC.
文摘There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.
文摘A new architecture of CMOS low voltage downconve rsion mixer is presented.With 1.452GHz LO input and 1.45GHz RF input,simulation results show that the conversion gain is 15dB,IIP3 is -4.5dBm,NF is 17dB,the maximum transient power dissipation is 9.3mW,and DC power dissipation is 9.2mW.The mixer’s noise and linearity analyses are also presented.
