Design and comparison of new fault-tolerant majority gate based on quantum-dotcellular automata

Quantum-dot cellular automata(QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.

N×N Clos Digital Cross-Connect Switch Using Quantum Dot Cellular Automata(QCA)

Quantum dot cellular automata(QCA)technology is emerging as a future technology which designs the digital circuits at quantum levels.The tech-nology has gained popularity in terms of designing digital circuits,which occupy very less area and less power dissipation in comparison to the present comple-mentary metal oxide semiconductor(CMOS)technology.For designing the rou-ters at quantum levels with non-blocking capabilities various multi-stage networks have been proposed.This manuscript presents the design of the N×NClos switch matrix as a multistage interconnecting network using quantum-dot cellular automata technology.The design of the Clos switch matrix presented in the article uses three input majority gates(MG).To design the 4×4 Clos switch matrix,a basic 2×2 switch architecture has been proposed as a basic mod-ule.The 2×2 switching matrix(SM)design presented in the manuscript utilizes three input majority gates.Also,the 2×2 SM has been proposed usingfive input majority gates.Two different approaches(1&2)have been presented for designing 2×2 SM usingfive input majority gates.The 2×2 SM design based on three input majority gate utilizes four zone clocking scheme to allow signal transmis-sion.Although,the clocking scheme used in 2×2 SM using three input MG and in 2×2 SM approach 1 usingfive input MG is conventional.The 2×2 SM approach 2 design,utilizes the clocking scheme in which clocks can be applied by electricfield generators easily and in turn the switch element becomes physically realizable.The simulation results conclude that the 2×2 SM is suitable for designing a 4×4 Clos network.A higher order of input-output switching matrix,supporting more number of users can utilize the proposed designs.

Nanoscale cryptographic architecture design using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) based on cryptography is a new paradigm in the field of nanotechnology. The overall performance of QCA is high compared to traditional complementary metal-oxide semiconductor (CMOS) technology. To achieve data security during nanocommunication, a cryptography-based application is proposed. The devised circuit encrypts the input data and passes it to an output channel through a nanorouter cum data path selector, where the data is decrypted back to its original form. The results along with theoretical implication prove the accuracy of the circuit. Power dissipation and circuit complexity of the circuit have been analyzed.

An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata（QCA）. Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner.Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder（ESDBA）is 26% faster than the carry flow adder（CFA）-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder（EMDBA） performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead（CLA）-based BCD adder design. The proposed multi-digit adder produces significantly less delay of（N – 1）＋3.5 clock cycles compared to the N＊One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.