A Cascade H Bridge (CHB) is evaluated for both electric vehicle motor traction control and off-vehicle charging against the Power ElectronicsUK Automotive Challenge for cost and mass for the year 2035. By combining th...A Cascade H Bridge (CHB) is evaluated for both electric vehicle motor traction control and off-vehicle charging against the Power ElectronicsUK Automotive Challenge for cost and mass for the year 2035. By combining the power electronics with batteries using low-voltage MOSFET transistors in a series cascade arrangement the cost and mass targets could be met 12 years earlier (in 2023 and 20 times lighter if an application specific integrated circuit (ASIC) is used. A 200 kW peak reference car was used to evaluate cost and mass benefits using four different topologies of power electronics. Vehicle installation is shown to be simplified as only passive cooling is required removing the need for liquid cooling systems and the arrangement is inherently safe;no high voltages are present when the vehicle is stationary. The inherently higher efficiency of CHB increases vehicle range. The converter with integrated batteries can also behave as an integrated on-board battery charger delivering additional off-vehicle benefits by removing the need for costly external chargers.展开更多
为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优...为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优化删减图样,使得到的删减比特全为冻结比特,可以显著提高删减算法的纠错性能。同时,根据MLC单元错误的不对称性,采用码率自适应的码字对FLASH中MSB和LSB进行不等错误保护。仿真结果表明:当误帧率为310-时,优化缩短极化码较相同码长的LDPC码和基本缩短极化码分别约有3.72~5.89 d B和1.47~3.49 d B增益;相比基于同一码率的优化缩短极化码方案,不等错误保护的差错控制方案获得约0.25 d B增益。展开更多
为了进一步提升多级存储单元的纠错性能,提出了一种基于多级存储单元阈值电压分布的Polar码优化设计方法。针对多级存储单元的固有特性,该方法迭代计算各存储单元比特的巴氏参数值优化设计Polar码。分析了不同构造方法对多级存储单元闪...为了进一步提升多级存储单元的纠错性能,提出了一种基于多级存储单元阈值电压分布的Polar码优化设计方法。针对多级存储单元的固有特性,该方法迭代计算各存储单元比特的巴氏参数值优化设计Polar码。分析了不同构造方法对多级存储单元闪存性能的影响,并与文中所构造的Polar码和系统Polar码在多级存储单元信道中的性能进行了比较。仿真结果表明:在多级存储单元信道中,当误码率为10^(-5)时,本文所构造的Polar码与高斯信道下经典巴氏参数法构造的Polar码相比可获得约2 d B增益;当信噪比为21 d B时,与蒙特卡罗法构造的Polar码相比,文中设计的系统Polar码的误码率可提升2个数量级。展开更多
文摘A Cascade H Bridge (CHB) is evaluated for both electric vehicle motor traction control and off-vehicle charging against the Power ElectronicsUK Automotive Challenge for cost and mass for the year 2035. By combining the power electronics with batteries using low-voltage MOSFET transistors in a series cascade arrangement the cost and mass targets could be met 12 years earlier (in 2023 and 20 times lighter if an application specific integrated circuit (ASIC) is used. A 200 kW peak reference car was used to evaluate cost and mass benefits using four different topologies of power electronics. Vehicle installation is shown to be simplified as only passive cooling is required removing the need for liquid cooling systems and the arrangement is inherently safe;no high voltages are present when the vehicle is stationary. The inherently higher efficiency of CHB increases vehicle range. The converter with integrated batteries can also behave as an integrated on-board battery charger delivering additional off-vehicle benefits by removing the need for costly external chargers.
文摘为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优化删减图样,使得到的删减比特全为冻结比特,可以显著提高删减算法的纠错性能。同时,根据MLC单元错误的不对称性,采用码率自适应的码字对FLASH中MSB和LSB进行不等错误保护。仿真结果表明:当误帧率为310-时,优化缩短极化码较相同码长的LDPC码和基本缩短极化码分别约有3.72~5.89 d B和1.47~3.49 d B增益;相比基于同一码率的优化缩短极化码方案,不等错误保护的差错控制方案获得约0.25 d B增益。
文摘为了进一步提升多级存储单元的纠错性能,提出了一种基于多级存储单元阈值电压分布的Polar码优化设计方法。针对多级存储单元的固有特性,该方法迭代计算各存储单元比特的巴氏参数值优化设计Polar码。分析了不同构造方法对多级存储单元闪存性能的影响,并与文中所构造的Polar码和系统Polar码在多级存储单元信道中的性能进行了比较。仿真结果表明:在多级存储单元信道中,当误码率为10^(-5)时,本文所构造的Polar码与高斯信道下经典巴氏参数法构造的Polar码相比可获得约2 d B增益;当信噪比为21 d B时,与蒙特卡罗法构造的Polar码相比,文中设计的系统Polar码的误码率可提升2个数量级。
