A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the convent...A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.展开更多
Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-ba...Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.展开更多
For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the r...For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.展开更多
In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtua...In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.展开更多
Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comp...Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.展开更多
提出了一种应用于音频应用的Zoom型模数转换器,采用一个5位异步逐次逼近式(Successive Approximation Register,SAR)模拟数字转换器(Analog to Digital Converter,ADC)与3阶多位量化离散时间的Delta-Sigma调制器相结合,通过SAR ADC进行...提出了一种应用于音频应用的Zoom型模数转换器,采用一个5位异步逐次逼近式(Successive Approximation Register,SAR)模拟数字转换器(Analog to Digital Converter,ADC)与3阶多位量化离散时间的Delta-Sigma调制器相结合,通过SAR ADC进行粗量化、Delta-Sigma调制器进行精细量化的方式,实现高的动态范围和精度。该Zoom型模数转换器采用0.18μm CMOS工艺实现,仿真结果表明,在1.8 V电源电压和3.072 MHz采样频率下,实现了109.34 dB的信号噪声失真比(Signalto-Noise-and-Distortion Ratio,SNDR),17.87 bits的有效位数(Effective Number of Bits,ENOB),112.7 dB的动态范围(Dynamic Range,DR),整体电路功耗为3.73 mW。展开更多
基金Project supported by the 2nd Stage of Brain KoreaProject supported by the Korea Research Foundation
文摘A multi-bit antifuse-type one-time programmable （OTP） memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS （complementary metal-oxide semiconductor） process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm× 327 μ,, and the read current is simulated to be 30.4 μA.
文摘Differential detection of continuous phase modulation suffers from significant intersymbol interference. To reduce bit error rate, multi-branch fractional multi-bit differential detection (MFMDD) with decision feed-back is proposed. By introducing decision feedback in multi-bit differential detected signals, severe inter-symbol interference can be removed. Simulation results show that the proposed structure can greatly im-proves the performance compared with MFMDD without decision feedback, and the performance of 9 FMDD is very near to the performance of the coherent detection.
文摘For the processor working in the radiation environment in space, it tends to suffer from the single event effect on circuits and system failures, due to cosmic rays and high energy particle radiation. Therefore, the reliability of the processor has become an increasingly serious issue. The BCH-based error correction code can correct multibit errors, but it introduces large latency overhead. This paper proposes a hybrid error correction approach that combines BCH and EDAC to correct both multi-bit and single-bit errors for caches with low cost. The proposed technique can correct up to four-bit error, and correct single-bit error in one cycle. Evaluation results show that, the proposed hybrid error-correction scheme can improve the performance of cache accesses up to 20% compared to the pure BCH scheme.
基金Project supported by the National Basic Research Program of China(No.2006CB302700)
文摘In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.
文摘Over the last few decades, several all-optical circuits have been proposed to meet the need of high-speed data processing. In some information processing architectures, the role of various analog and digital data comparisons is very important. In this letter, we proposed a multi-bit data comparison scheme. The scheme is based on the switching property of optical nonlinear material. Ultrafast operational speed larger than gigahertz can be expected from this all-optical scheme.
文摘提出了一种应用于音频应用的Zoom型模数转换器,采用一个5位异步逐次逼近式(Successive Approximation Register,SAR)模拟数字转换器(Analog to Digital Converter,ADC)与3阶多位量化离散时间的Delta-Sigma调制器相结合,通过SAR ADC进行粗量化、Delta-Sigma调制器进行精细量化的方式,实现高的动态范围和精度。该Zoom型模数转换器采用0.18μm CMOS工艺实现,仿真结果表明,在1.8 V电源电压和3.072 MHz采样频率下,实现了109.34 dB的信号噪声失真比(Signalto-Noise-and-Distortion Ratio,SNDR),17.87 bits的有效位数(Effective Number of Bits,ENOB),112.7 dB的动态范围(Dynamic Range,DR),整体电路功耗为3.73 mW。
