A Sensor-less Surface Mounted PMSM for Electronic Speed Control in Multilevel Inverter

Recent advancements in power electronics technology evolves inverter fed electric motors.Speed signals and rotor position are essential for controlling an electric motor accurately.In this paper,the sensorless speed control of surface-mounted permanent magnet synchronous motor(SPMSM)has been attempted.SPMSM wants a digital inverter for its precise working.Hence,this study incor-poratesfifteen level inverter to the SPMSM.A sliding mode observer(SMO)based sensorless speed control scheme is projected to determine rotor spot and speed of the multilevel inverter(MLI)fed SPMSM.MLI has been operated using a multi carrier pulse width modulation(MCPWM)strategy for generation offif-teen level voltages.The simulation works are executed with MATLAB/SIMU-LINK software.The steadiness and the heftiness of the projected model have been investigated under no loaded and loaded situations of SPMSM.Furthermore,the projected method can be adapted for electric vehicles.

Minimization of Switching Devices and Driver Circuits in Multilevel Inverter

The various configurations of multilevel inverter involve the use of more numbers of switching devices, energy storage devices and/or unidirectional devices. Each switching unit necessitates the add-on driver circuit for proper functionality. Cascaded H-Bridge Multilevel Inverter requires overlapped switching pulses for the switching devices in positive and negative arms of the bridge which may lead to short circuit during the device failure. This work addresses the problems in different configurations of multilevel inverter by using reduced number of switching and energy storage devices and driver circuits. In the present approach Single Switch is used for each stair case positive output and single H-Bridge for phase reversal. Driver circuits are reduced by using the property of body diode of the MOSFET. Switching pulses are generated by Arduino Development Board. The circuit is simulated using Matlab. More so, through experimental means, it is physically tested and results are analyzed for the 5-step inverter and thereby simulation is fully validated. Consequently, cycloconverter operation of the circuit is simulated using Matlab. Moreover, half bridge configuration of the multilevel inverter is also analyzed for high frequency induction heating applications.

Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications

This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.

Applications of cascade multilevel inverters

Cascade multilevel inverters have been developed for electric utility applications. A cascade M level inverter consists of (M 1)/2 H bridges in which each bridge's dc voltage is supported by its own dc capacitor. The new inverter can: (1) generate almost sinusoidal waveform voltage while only switching one time per fundamental cycle; (2) dispense with multi pulse inverters' transformers used in conventional utility interfaces and static var compensators; (3) enables direct parallel or series transformer less connection to medium and high voltage power systems. In short, the cascade inverter is much more efficient and suitable for utility applications than traditional multi pulse and pulse width modulation (PWM) inverters. The authors have experimentally demonstrated the superiority of the new inverter for power supply, (hybrid) electric vehicle (EV) motor drive, reactive power (var) and harmonic compensation. This paper summarizes the features, feasibility, and control schemes of the cascade inverter for utility applications including utility interface of renewable energy, voltage regulation, var compensation, and harmonic filtering in power systems. Analytical, simulated, and experimental results demonstrated the superiority of the new inverters.

Analysis of Reduced Switch Topology Multilevel Inverter with Different Pulse Width Modulation Technique and Its Application with DSTATCOM

Multilevel inverter has played a vital role in medium and high power applications in the recent years. In this paper, Reduced Switch Count Multi Level Inverter structure (RSCMLI) topology is presented with different pulse width modulation techniques. The harmonic level analysis is carried out for the reduced switch count multilevel inverter with the different PWM technique such as with Alternate Phase Opposition Disposition (APOD) method, In Phase Disposition (IPD) method and multi reference pulse width modulation method for five level, seven level , nine level and eleven level inverter. The simulation results are compared with the cascaded H Bridge Multi Level Inverter (CHBMLI). The nine level RSCMLI inverter with APOD method is used for the Distribution Static Synchronous Compensator (DSTATCOM) application in the nonlinear load connected system for power factor improvement. The result shows that the harmonic level and the number of switches required for RSCMLI is reduced compared to CHBMLI. RSCMLI employed in DSTATCOM improves the power factor and harmonic level of the system when it is connected to the nonlinear load.

A Novel Topology of Hybrid Multilevel Inverter with Minimum Number of Separated DC Sources

Multilevel inverter has become increasingly popular in recent years due to advantages of high power quality waveforms, low switching losses, and high-voltage capability. A novel multilevel inverter with minimum number of separated DC sources is presented in this paper. Three-phase output voltages of this inverter can easily be balanced because they are synthesized by using the same DC sources. A harmonic reduction method eliminating both the 5th and 7th harmonics is proposed. Finally, comparison results and spectral analysis are presented. Key words multilevel inverter - topology - DC source - harmonic reduction - spectrum Project supported by the Postdoctoral Science Foundation of Shanghai (Grant No. kO7)

A Space Vector PWM Scheme for Multilevel Inverters Based on Two-Level Space Vector PWM

Ⅰ. INTRODUCTION MULTILEVEL inverters are increasingly being used in high-power medium voltage applications due to their superior performance compared to two-level inverters, such as lower common-mode voltage, lower dv/dt, lower harmonics in output voltage and current, and reduced voltage on the power switches.

Intelligent-Based Maximum Power Extraction on Grid-Integrated Multilevel Inverter-Fed Wind-Driven Induction Generators

This paper presents an intelligent controller employing Adaptive Neuro-Fuzzy Inference System (ANFIS) for extracting maximum power from the wind energy conversion system even during the change in the wind speed conditions with improved quality of power. The proposed induction generator with multilevel inverter along with intelligent controller based Maximum Power Point Tracking (MPPT) technique aims at integrating winds system with improved maximum power injection and minimum harmonic issues. The proposed method will improve the power quality which is delivered to the grid in terms of harmonic, and inject the maximum power to the grid. To validate the effectiveness of the proposed control strategy, ANFIS controller, Fuzzy Inference System (FIS) and without MPPT controller have been presented and tested using MATLAB/Simulink environment.

Hybrid Control Strategy for BCD Topology Based Modular Multilevel Inverter

In this paper, a Binary Coded Decimal (BCD) topology of modular multilevel inverter with reduced component count is proposed. For the control of this inverter, hybrid control strategy is used. The proposed modular multilevel inverter uses asymmetrical dc sources and reduced number of switches topology. This hybrid modulation technique uses the multicarrier based Pulse Width Modulation (PWM) and the fundamental frequency modulation strategy. The hybrid modulation algorithm is implemented with “NUC140” micro-controller. In comparison with the conventional and some of the recently reported inverter topologies, the proposed inverter topology is able to generate high number of voltage levels in the output by using minimum number of components such as dc sources, power switches and driver circuits. This inverter offers significant performance with less number of components. The feasibility of the proposed topology is confirmed by simulation and experimental results.

A Novel Asymmetrical Single-Phase Multilevel Inverter Suitable for Hybrid Renewable Energy Sources

This paper introduces a novel single-phase asymmetrical multilevel inverter suitable for hybrid renewable energy sources. The proposed inverter consists of two isolated DC sources and six power semiconductor controlled switches. The suggested inverter is capable of generating seven-level output when the input DC voltage is taken in the ratio of 1:2. The higher magnitude DC source is fed from Photo Voltaic (PV) panels, whereas the lower magnitude DC source is fed from Wind Turbine (WT) driven Permanent Magnet DC (PMDC) generator. Both the renewable energy sources are connected to the inverter via two DC-DC boost converters connected in cascade (i.e. one for maximum power point tracking and another for DC-link voltage control). The proposed hybrid renewable energy source inverter is connected to single-phase grid via proper control systems. The complete system is simulated using MATLAB/SIMULINK and the results are presented in detail.

Harmonic Minimization in Seven-Level Cascaded Multilevel Inverter Using Evolutionary Algorithm

Inverters are power electronic devices that change over DC to sinusoidal AC quantity. Be that as it may, in down to earth, these devices produce non-sinusoidal yield which contains harmonics, so as to blend a close sinusoidal component and to lessen the harmonic distortion multilevel inverters developed. Mathematical methods, which were developed, are derivative based and need initial considerations. To overcome this, evolutionary algorithms, which are derivative free and accurate, were developed for obtaining multi levels of output voltage. The proposed work uses two evolutionary algorithms, namely, Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) algorithm. These algorithms are used to generate the switching angles by satisfying the non linear transcendental equations that govern the low order harmonic components. A seven level cascaded full bridge inverter is designed using MATLAB/Simulink and the results validate the results for switching angles. The Total Harmonic Distortion (THD) value obtained for GA and PSO is 11.81% and 10.84% respectively. The solution obtained from GA algorithm was implemented in hardware using dsPIC controller to validate the simulation results. The THD value obtained for cascaded seven-level multilevel inverter in the hardware prototype is 25.9%.

Analysis of Symmetrical and Asymmetrical Current Source Multilevel Inverter

The paper proposes a Current Source Multilevel Inverter (CSMLI) with single rating inductor topology. Multilevel inverters are most familiar with power converter’s applications due to reduced dv/dt, di/dt stress, and very efficient for reducing harmonic distortion in the output voltage and output current. The proposed nine-level current source inverter has been tested under symmetrical and asymmetrical modes of operation, and their activities are compared using PI and Fuzzy PI (Proportional Integral) controllers with multicarrier PWM (Pulse Width Modulation) strategy. MATLAB/Simulink simulation has been made for the proposed converter to obtain its performance measures. Some experimental results are given to verify the presented Current Source Multilevel Inverter.

Asymmetric Three-Phase Cascading Trinary-DC Source Multilevel Inverter Topologies for Variable Frequency PWM

Asymmetric three-phase cascading Trinary-DC source Multilevel Inverter which can achieve reduced harmonics and superior root mean square (RMS) values of the output voltage is proposed. This topology can achieve cascaded full bridge inverter operation with dissimilar (unequal) DC Source and it is fired by using variable frequency pulse with modulation technique as a switching strategy. This pulse width modulation switching strategy has a newly adopted multicarrier single reference technique. The performance parameter factors like Form Factor (FF), Crest Factor (CF), Total Harmonic Distortion (THD) and fundamental RMS output voltage (VRMS) are estimated by using proposed asymmetrical three-phase cascading multilevel inverter for several modulation indices (0.8 - 1). The research study carries with MATLAB/SIMULINK based simulation and experimental results obtained using appropriate prototype (test board) to prove the viability of the proposed concept.

Modular Multilevel Inverter with Maximum Power Point Tracking for Grid Connected Photovoltaic Application

A single-phase modular multilevel inverter based photovoltaic system for grid connection is proposed. This photovoltaic system utilizes two conversion stages： a boost converter for tracking the maximum power point and a modular multilevel inverter used as an interfacing unit. The maximum power point tracking is achieved with a fuzzy logic controller, and the modular multilevel inverter regulates the DC link voltage and synchronizes the grid voltage and current in order to achieve unity power factor operation. The proposed system provides high dynamic performance and power quality injected into the grid. The validity of the proposed system is confirmed by simulations.

Harmonic Minimization in Seven Level Cascaded Multilevel Inverter Using Selective Harmonic Elimination PWM Techniques

This paper concentrates on enhancing the productivity of the multilevel inverter and nature of yield voltage waveform. Seven level lessened switches topology has been actualized with just seven switches. Essential Switching plan and Selective Harmonics Elimination were executed to diminish the Total Harmonics Distortion (THD) esteem. Selective Harmonics Elimination Stepped Waveform (SHESW) strategy is executed to dispense with the lower order harmonics. Fundamental switching plan is utilized to control the switches in the inverter. The proposed topology is reasonable for any number of levels. The harmonic lessening is accomplished by selecting fitting switching angles. It indicates would like to decrease starting expense and unpredictability consequently it is able for modern applications. In this paper, third and fifth level harmonics have been disposed of. Simulation work is done utilizing the MATLAB/Simulink programming results have been displayed to accept the hypothesis.

High-Power-Factor Adjustable Speed Drive Using Diode Clamped Multilevel Inverter

This paper presents a new approach to alleviate the harmonics and to enhance the power factor of the ASD （adjustable speed drive）. A conventional ASD with 2-level PWM （pulse width modulation） inverters generate high dv/dt and high frequency common mode voltages which are harmful for the drive applications. It reduces the motor bearings life and conducted EMI （electro magnetic interference） deteriorates the insulation. In this paper, a diode clamped multilevel （3-level） inverter is used to perform dual task. It generates HF （high frequency） current to be injected at the input of the three-phase front-end rectifier thereby improving the harmonic spectra and the power factor. It also drives the induction motor. The salient feature of this paper is that it does not require separate converters for improving power factor and to drive induction motor. Furthermore, inverter switches operate with ZVS （zero voltage switching）, thus reducing the switching losses substantially, The voltage stress of the switches also has been reduced to half of the conventional 2-level converter. The inverter is operated with SPWM （sinusoidal pulse width modulation） technique. The simulation results for a prototype of 2.2 kW are presented.

A Novel Multilevel Inverter Employing Additive and Subtractive Topology

As the demand for high voltage, high power inverters are increasing and there is a problem of connecting a power semiconductor switch directly to a high voltage network. As a part of this the multilevel inverters had been introduced. As a part of this, several researches had been done for the development of multilevel inverters. The commercially available and extensively studied topologies for multilevel voltage output are Neutral Point Clamped (NPC), Cascaded Half Bridge (CHB) and Flying Capacitor (FC) converters. However, with these existing topologies, there is a significant increase in the number of power switches and passive components. Thus it leads to more complex control circuitry and overall cost of the system increase with increase in the output levels. In this paper, a novel multilevel inverter is proposed in which it employs additive and subtractive topology to get higher output levels. This approach significantly reduces the number of power switches needed as compared to existing topology. The present developed multilevel inverter can generate only five voltage levels. With this proposed topology the multilevel inverter can be modified to nine-level inverter. Moreover modified hybrid multicarrier Pulse Width Modulation (PWM) technique can be implemented in the proposed multilevel inverter in order to obtain uniform switch utilization and lower THD. An appropriate modulation scheme is presented and also the proposed concept is analyzed through simulation studies.

State Space Modeling and Implementation of a New Transformer Based Multilevel Inverter Topology with Reduced Switch Count

This paper presents a new transformer based multilevel inverter, with a novel pulse width modulation scheme to achieve seven-level inverter output voltage. The proposed inverter switching pattern consists of three fundamental frequency sinusoidal reference signals with an offset value, and one high frequency triangular carrier signal. This switching scheme has been implemented using an 8-bit Xilinx SPARTAN-3E field programmable gate array based controller. In addition, the state space model of the proposed inverter is developed. The significant features of the proposed topology are: reduction of the power switch count and the gate drive power supply unit, the provision of a galvanic isolation between load and sources by a centre tap transformer. An exhaustive comparison has been made of the existing multilevel inverter topologies and the proposed topology. The performances of the proposed topology with resistive, resistive-inductive loads are simulated in a MATLAB environment and validated experimentally on a laboratory prototype.

Modeling and Analysis of Variable Frequency Inverted Sine PWM Technique for a Hybrid Cascaded Multilevel Inverter

In cascaded H-bridge multilevel inverter, a variable frequency inverted sine PWM technique is modeled for hybrid electric vehicles. It has a particular advantage of increasing power which is achieved using series connection of H-bridge and also this topology is capable to produce superior spectral quality with considerable improvement of fundamental voltage. The variable frequency inverted sine PWM technique produces lesser torque ripple and enhances the fundamental output voltage mainly at lower modulation index ranges. The topologies of multilevel inverter are flying capacitor, diode clamped and cascaded inverter. In the paper, we will discuss about the cascaded multilevel inverter based on inverted sine PWM technique. The two switching strategies widely used to control multilevel inverters are constant frequency inverted sine PWM (CF-ISPWM) and variable frequency inverted sine PWM (VF-ISPWM). This implies that switch utilization substantially reduces 32.35% of the constant frequency inverted sine PWM switching technique. The performance of the technique is validated in terms of Total Harmonic Distortion (THD) and Torque ripple which significantly reduces when compared to constant frequency ISPWM. The analysis of conventional triangular PWM inverter and inverted sine PWM inverter using constant and variable switching scheme is done in MATLAB Simulink and verified experimentally by FPGA Spartan 3E processor.

Performance Metric of Z Source CHB Multilevel Inverter FED IM for Selective Harmonic Elimination and THD Reduction

This paper focuses on a Z source cascaded multilevel inverter which is designed to minimize harmonics in the output voltage. A balanced dc-link peak voltage can be achieved. The power generation module is built by PV panels which are connected to Z-Source Cascade H-bridge inverter. Cascaded multilevel inverter can achieve the distributed maximum power point tracking to increase the system efficiency and achieve high voltage/high power grid tie without a transformer. This paper analyzes the different PWM switching scheme and the operating states of a ZSI module and comparison is made with different PWM and total harmonic distortion of various PWM schemes.