Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication.Therefore,high-speed and low-power multipliers design is mandatory for efficient computing systems.In designing low-energy dissipation circuits,reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity.This paper introduces an efficient signed/unsigned 4×4 reversible Vedic multiplier with minimum quantum cost.The Vedic multiplier is considered fast as it generates all partial product and their sum in one step.This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output.First,the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam(UT)Sutra.This multiplier consists of bitwise multiplication and adder compressors.Compared with Vedic multipliers in the literature,the proposed design has a quantum cost of 111 with a reduction of 94%compared to the previous design.It has a garbage output of 30 with optimization of the best-compared design.Second,the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers.Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters.DesignI has separate binary two’s complement(B2C)and MUX circuits,while DesignII combines binary two’s complement and MUX circuits in one circuit.DesignI shows the lowest quantum cost,231,regarding state-ofthe-art.DesignII has a quantum cost of 199,reducing to 86.14%of DesignI.The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.

CHARACTERIZATION OF RESIDUATED LATTICES VIA MULTIPLIERS

In the paper,we introduce some of multipliers on residuated lattices and investigate the relations among them.First,basing on the properties of multipliers,we show that the set of all multiplicative multipliers on a residuated lattice A forms a residuated lattice which is isomorphic to A.Second,we prove that the set of all total multipliers on A is a Boolean subalgebra of the residuated lattice(which is constituted by all multiplicative multipliers on A)and is isomorphic to the Boolean center of A.Moreover,by partial multipliers,we study the maximal residuated lattices of quotients for residuated lattices.Finally,we focus on principal implicative multipliers on residuated lattices and obtain that the set of principal implicative multipliers on A is isomorphic to the set of all multiplicative multipliers on A under the opposite(dual)order.

FPGA Optimized Accelerator of DCNN with Fast Data Readout and Multiplier Sharing Strategy

With the continuous development of deep learning,Deep Convolutional Neural Network(DCNN)has attracted wide attention in the industry due to its high accuracy in image classification.Compared with other DCNN hard-ware deployment platforms,Field Programmable Gate Array(FPGA)has the advantages of being programmable,low power consumption,parallelism,and low cost.However,the enormous amount of calculation of DCNN and the limited logic capacity of FPGA restrict the energy efficiency of the DCNN accelerator.The traditional sequential sliding window method can improve the throughput of the DCNN accelerator by data multiplexing,but this method’s data multiplexing rate is low because it repeatedly reads the data between rows.This paper proposes a fast data readout strategy via the circular sliding window data reading method,it can improve the multiplexing rate of data between rows by optimizing the memory access order of input data.In addition,the multiplication bit width of the DCNN accelerator is much smaller than that of the Digital Signal Processing(DSP)on the FPGA,which means that there will be a waste of resources if a multiplication uses a single DSP.A multiplier sharing strategy is proposed,the multiplier of the accelerator is customized so that a single DSP block can complete multiple groups of 4,6,and 8-bit signed multiplication in parallel.Finally,based on two strategies of appeal,an FPGA optimized accelerator is proposed.The accelerator is customized by Verilog language and deployed on Xilinx VCU118.When the accelerator recognizes the CIRFAR-10 dataset,its energy efficiency is 39.98 GOPS/W,which provides 1.73×speedup energy efficiency over previous DCNN FPGA accelerators.When the accelerator recognizes the IMAGENET dataset,its energy efficiency is 41.12 GOPS/W,which shows 1.28×−3.14×energy efficiency compared with others.

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popularfield for low power consumption that is used in several applications like image processing,video processing,multi-media and data mining.This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier.The multiplier is the most essen-tial element used for approximate computing where the power consumption is majorly based on its performance.There are several researchers are worked on the approximate multiplier for power reduction for a few decades,but the design of low power approximate multiplier is not so easy.This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy.To overcome these issues,the digital circuits are applied to the Deep Learning(DL)approaches for higher accuracy.In recent times,DL is the method that is used for higher learning and prediction accuracy in severalfields.Therefore,the Long Short-Term Memory(LSTM)is a popular time series DL method is used in this work for approximate computing.To provide an optimal solution,the LSTM is combined with a meta-heuristics Jel-lyfish search optimisation technique to design an input aware deep learning-based approximate multiplier(DLAM).In this work,the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier.The optimal hyperparameters of the LSTM model are identified by jelly search opti-misation.Thisfine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy.The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a func-tion of area,delay,power and error metrics.The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approx-imate computing multiplier achieved a superior area and power reduction with very good results on error rates.

Bus Encoded LUT Multiplier for Portable Biomedical Therapeutic Devices

DSP operation in a Biomedical related therapeutic hardware need to beperformed with high accuracy and with high speed. Portable DSP hardware’s likepulse/heart beat detectors must perform with reduced operational power due to lack ofconventional power sources. This work proposes a hybrid biomedical hardware chip inwhich the speed and power utilization factors are greatly improved. Multipliers are thecore operational unit of any DSP SoC. This work proposes a LUT based unsignedmultiplication which is proven to be efficient in terms of high operating speed. For n bitinput multiplication n*n memory array of 2 n bit size is required to memorize all thepossible input and output combination. Various literature works claims to be achieve highspeed multiplication with reduced LUT size by integrating a barrel shifter mechanism.This paper work address this problem, by reworking the multiplier architecture with aparallel operating pre-processing unit which used to change the multiplier and multiplicandorder with respect to the number of computational addition and subtraction stages required.Along with LUT multiplier a low power bus encoding scheme is integrated to limit the powerconstraint of the on chip DSP unit. This paper address both the speed and power optimizationtechniques and tested with various FPGA device families.

ON SOME GENERALIZED DIFFERENCE PARANORMED SEQUENCE SPACES ASSOCIATED WITH MULTIPLIER SEQUENCE DEFINED BY MODULUS FUNCTION

In this article we introduce the paranormed sequence spaces （f,A, Am,p）, c0（f,A,Am,p） and L00（f,A, Am,p）, associated with the multiplier sequence ∧ = （hk）, defined by a modulus function f. We study their different properties like solidness, symmetricity, completeness etc. and prove some inclusion results.

Images of triple gas electron multiplier with pixel-pads

Testing of a triple gas electron multiplier （GEM） with pixel-pads is described. Images by scanning and suspending radioactive sources were obtained by using 96 channels digital data acquisition （DAQ） system which was composed of 96 8×8 mm2 pads and associated electronics channels.

Missile robust gain scheduling autopilot design using full block multipliers

Reduction of conservatism is one of the key and difficult problems in missile robust gain scheduling autopilot design based on multipliers.This article presents a scheme of adopting linear parameter-varying（LPV） control approach with full block multipliers to design a missile robust gain scheduling autopilot in order to eliminate conservatism.A model matching design structure with a high demand on matching precision is constructed based on the missile linear fractional transformation（LFT） model.By applying full block S-procedure and elimination lemma,a convex feasibility problem with an infinite number of constraints is formulated to satisfy robust quadratic performance specifications.Then a grid method is adopted to transform the infinite-dimensional convex feasibility problem into a solvable finite-dimensional convex feasibility problem,based on which a gain scheduling controller with linear fractional dependence on the flight Mach number and altitude is derived.Static and dynamic simulation results show the effectiveness and feasibility of the proposed scheme.

Reconstruction of electrical capacitance tomography images based on fast linearized alternating direction method of multipliers for two-phase flow system

Electrical capacitance tomography(ECT)has been applied to two-phase flow measurement in recent years.Image reconstruction algorithms play an important role in the successful applications of ECT.To solve the ill-posed and nonlinear inverse problem of ECT image reconstruction,a new ECT image reconstruction method based on fast linearized alternating direction method of multipliers(FLADMM)is proposed in this paper.On the basis of theoretical analysis of compressed sensing(CS),the data acquisition of ECT is regarded as a linear measurement process of permittivity distribution signal of pipe section.A new measurement matrix is designed and L1 regularization method is used to convert ECT inverse problem to a convex relaxation problem which contains prior knowledge.A new fast alternating direction method of multipliers which contained linearized idea is employed to minimize the objective function.Simulation data and experimental results indicate that compared with other methods,the quality and speed of reconstructed images are markedly improved.Also,the dynamic experimental results indicate that the proposed algorithm can ful fill the real-time requirement of ECT systems in the application.

MULTIPLIERS AND RELATIVE COMPLETION IN WEIGHTED LORENTZ SPACES

Let G be a locally compact Abelian group with Haar measure μ. In the present paper, first the authors discussed some properties of weighted Lorentz space. Then they defined the relative completion A of a subspace A of the weighted Lorentz space, and showed that the space of the multipliers from L_w~1,(G) to A is algebrically isomorphic and homeomorphic to A.

CHARACTERIZATION OF MULTIPLIER SPACES WITH DAUBECHIES WAVELETS

We characterize the multiplier spaces from Sobolev spaces to L2 with Daubechles wavelets without using capacity.

CARLESON MEASURES,RIEMANN-STIELTJES OPERATORS AND MULTIPLIERS ON F(p,q,s)SPACES IN THE UNIT BALL OF C^n

This paper is devoted to characterizing the Riemann-Stieltjes operators and pointwise multipliers on F（p, q, s） spaces in the unit ball of C^n which contain many classical function spaces, such as the Bloch space, BMOA and Q8 spaces. The boundedness and compactness of these operators on F（p, q, s） spaces are characterized by means of an embedding theorem, i.e., F（p,q, s） spaces boundedly embedded into the tent-type spaces Tp,s^∞（μ）

MULTIPLIERS AND TENSOR PRODUCTS OF WEIGHTED L^p-SPACES

Let G be a locally compact unimodular group with Haar measure rmdx and ω be the Beurling's weight function on G (Reiter, [10]). In this paper the authors define a space Aωp,q (G) and prove that Aωp,q (G) is a translation invariant Banach space. Fur- thermore the authors discuss inclusion properties and show that if G is a locally compact abelian group then Aωp,q (G) admits an approximate identity bounded in Lω1 (G). It is also proved that the space Lωp (G) Lω1 Lωq (G) is isometrically isomorphic to the space Aωp,q (G) and the space of multipliers from Lωp (G) to Lq-1, (G) is isometrically isomorphic to the dual of the space Aωp,q (G) iff G satisfies a property Ppq. At the end of this work it is showed that if G is a locally compact abelian group then the space of all multipliers from Lω1 (G) to Aωp,q (G) is the space Aωp,q (G).

MULTIPLIERS ON HERZ TYPE HARDY SPACES OVER LOCAL FIELDS

In this paper, we establish two multiplier theorems for Herz type Hardy spaces, and as an application, we discuss the boundedness of pseudo-differential operators in these spaces.

SOME MULTIPLIER THEOREMS FOR ANISOTROPIC HARDY SPACES——In Memory of Professor Yongsheng Sun

Let A be a symmetric expansive matrix and H^p（R^n） be the anisotropic Hardy space associated with A. For a function m in L∞（R^n）, an appropriately chosen function η in Cc^∞（R^n） and j ∈ Z define mj（ξ） = m（A^jξ）η（ξ）. The authors show that if 0 〈 p 〈 1 and mj belongs to the anisotropic nonhomogeneous Herz space K1^1/P^-1,p（R^n）, then m is a Fourier multiplier from H^p（R^n） to L^V（R^n）. For p = 1, a similar result is obtained if the space K1^0.1（R^n） is replaced by a slightly smaller space K（w）. Moreover, the authors show that if 0 〈 p 〈 1 and if the sequence {（mj）^v} belongs to a certain mixednorm space, depending on p, then m is also a Fourier multiplier from H^p（R^n） to L^v（R^n）.

Distributed Lagrange Multiplier/Fictitious Domain Finite Element Method for a Transient Stokes Interface Problem with Jump Coefficients

The distributed Lagrange multiplier/fictitious domain(DLM/FD)-mixed finite element method is developed and analyzed in this paper for a transient Stokes interface problem with jump coefficients.The semi-and fully discrete DLM/FD-mixed finite element scheme are developed for the first time for this problem with a moving interface,where the arbitrary Lagrangian-Eulerian(ALE)technique is employed to deal with the moving and immersed subdomain.Stability and optimal convergence properties are obtained for both schemes.Numerical experiments are carried out for different scenarios of jump coefficients,and all theoretical results are validated.

OPERATOR-VALUED FOURIER MULTIPLIER THEOREMS ON TRIEBEL SPACES

The authors establish operator-valued Fourier multiplier theorems on Triebel spaces on R^N, where the required smoothness of the multiplier functions depends on the dimension N and the indices of the Triebel spaces. This is used to give a sufficient condition of the maximal regularity in the sense of Triebel spaces for vector-valued Cauchy problems with Dirichlet boundary conditions.

EXTENDED CESRO OPERATORS AND MULTIPLIERS ON BMOA

In this article, we characterize the boundedness and compactness of extended Cesaro operators on the spaces BMOA by the Carleson measures in the unit ball. Mea while, we study the pointwise multipliers on BMOA.

MULTIPLIER OPERATORS AND EXTREMAL FUNCTIONS RELATED TO THE DUAL DUNKL-SONINE OPERATOR

We study the dual Dunkl-Sonine operator tSk,e on Rd and give expression of tSk,t, using Dunkl multiplier operators on Rd, Next, we study the extremal functions fλ, λ〉 0 related to the Dunkl multiplier operators, and more precisely show that {fλ}λ〉0 converges uniformly to tSk,e（f） as λ→0 Certain examples based on Dunkl-heat and Dunkt-Poisson kernels are provided to illustrate the results.

L-R smash products for multiplier Hopf algebras

The theory of L-R smash product is extended to multiplier Hopf algebras and a sufficient condition for L-R smash product to be regular multiplier Hopf algebras is given. In particular, the result of the paper implies Delvaux＇s main theorem in the case of smash products.