Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing ga...Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.展开更多
纳米工艺水平下,负偏置温度不稳定性(negative bias temperature instability,NBTI)成为影响集成电路可靠性的关键性因素。NBTI效应会导致晶体管阈值电压增加,老化加剧,最终导致电路时序违规。为了缓解电路的NBTI效应,引入考虑门的时延...纳米工艺水平下,负偏置温度不稳定性(negative bias temperature instability,NBTI)成为影响集成电路可靠性的关键性因素。NBTI效应会导致晶体管阈值电压增加,老化加剧,最终导致电路时序违规。为了缓解电路的NBTI效应,引入考虑门的时延关键性的权值识别关键门,通过比较关键门的不同扇入门替换后的时延增量,得到引入额外时延相对较小的双输入的需要替换的门,最后进行门替换。对基于45 nm晶体管工艺的ISCAS85基准电路实验结果显示,在电路时序余量为5%时,应用本文改进的门替换方法电路时延改善率为41.23%,而面积增加率和门替换率分别为3.17%和8.99%,明显优于传统门替换方法。展开更多
文摘Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.
文摘纳米工艺水平下,负偏置温度不稳定性(negative bias temperature instability,NBTI)成为影响集成电路可靠性的关键性因素。NBTI效应会导致晶体管阈值电压增加,老化加剧,最终导致电路时序违规。为了缓解电路的NBTI效应,引入考虑门的时延关键性的权值识别关键门,通过比较关键门的不同扇入门替换后的时延增量,得到引入额外时延相对较小的双输入的需要替换的门,最后进行门替换。对基于45 nm晶体管工艺的ISCAS85基准电路实验结果显示,在电路时序余量为5%时,应用本文改进的门替换方法电路时延改善率为41.23%,而面积增加率和门替换率分别为3.17%和8.99%,明显优于传统门替换方法。
