Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.

Characterization of the effects of nitrogen and hydrogen passivation on SiO2/4H-SiC interface by low temperature conductance measurements

We investigate the effects of NO annealing and forming gas （FG） annealing on the electrical properties of a SiO2/SiC interface by low-temperature conductance measurements. With nitrogen passivation, the density of interface states （DIT） is significantly reduced in the entire energy range, and the shift of flatband voltage, AVFB, is effectively suppressed to less than 0.4 V. However, very fast states are observed after NO annealing and the response frequencies are higher than 1 MHz at room temperature. After additional FG annealing, the DIT and AVFB are further reduced. The values of the DIT decrease to less than 1011 cm-2 eV- 1 for the energy range of Ec - ET 〉/0.4 eV. It is suggested that the fast states in shallow energy levels originated from the N atoms accumulating at the interface by NO annealing. Though FG annealing has a limited effect on these shallow traps, hydrogen can terminate the residual Si and C dangling bonds corresponding to traps at deep energy levels and improve the interface quality further. It is indicated that NO annealing in conjunction with FG annealing will be a better post-oxidation process method for high performance SiC MOSFETs.