This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place ...This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.展开更多
随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线...随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线性度的方法,并以一款分段式10 bit DAC为例,分别采用简码和传统的全码方法验证了它的微分非线性DNL与积分非线性INL。结果表明,简码测试和全码测试得到的DNL与INL曲线趋势一致,但简码测试效率高,仅占全码测试周期的1/8;另外简码测试减小了负载电阻温漂引入的误差,因此相比全码测试线性度的性能提高了0.1-0.2 LSB。展开更多
文摘This paper presents a high speed ROM-less direct digital frequency synthesizer （DDFS） which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic （CML） is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm^2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0℃.
文摘随着数模转化器（DAC）位数的增加,模拟量的步进值越来越小,数字万用表的精度和负载电阻的热效应成为影响DAC线性度测量的重要因素。基于分段式电流舵DAC的结构,结合其二进制和温度计译码电路的特点,从理论上提出了一种使用简码测试线性度的方法,并以一款分段式10 bit DAC为例,分别采用简码和传统的全码方法验证了它的微分非线性DNL与积分非线性INL。结果表明,简码测试和全码测试得到的DNL与INL曲线趋势一致,但简码测试效率高,仅占全码测试周期的1/8;另外简码测试减小了负载电阻温漂引入的误差,因此相比全码测试线性度的性能提高了0.1-0.2 LSB。
