Characterization of on-chip balun with patterned floating shield in 65 nm CMOS

A simple method of balun synthesis is proposed to estimate the balun structure in the operating frequency band.Then,a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations. In order to investigate the impact of the patterned floating shield（PFS）,the optimized baluns with and without PFS are fabricated in a 65 nm 1P6M CMOS process.The measurement results demonstrate that the PFS obviously improves the insertion loss（IL） in the frequency range and a linear improving trend appears smoothly.It is also found that the PFS gradually improves the phase balance as the frequency increases,while it has a very slight influence on the magnitude balance.To characterize the device＇s intrinsic power transfer ability,we propose a method to obtain the baluns＇ maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect.We also use the resistive coupling efficiency to characterize the shielding effect,and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement.It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier（LNA） and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm^2 die size.

On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.

High-intensity spatial-mode steerable frequency up-converter toward on-chip integration

Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.

一种用于微带半波振子天线的新型BALUN

通过将常规的空气板线BALUN微带化,从而建立一种新型微带BALUN。该BALUN引入一个并联谐振电路,可以有效补偿半波振子的串联电抗而实现微带半波振子带宽的最大化。采用此种BAL-UN设计制作了一个L波段微带偶极子天线单元。测试结果表明:该半波振子天线在21.8%的带宽内驻波比优于1.18,带内交叉极化优于-21 dB,接近理论最大设计带宽。

带有小型化Balun的C波段单片GaAs pHEMT单平衡电阻性混频器

本文介绍了一种带有小型化无源Balun的C波段单片GaAs pHEMT单平衡电阻性混频器。Balun采用集总一分布式结构，使其长度与常用2／4耦合线Balun相比缩小了11倍，大大降低了将无源Balun应用于C波段单片集成电路中所需的芯片尺寸。混频器采用单平衡电阻性结构，在零功耗的情况下实现了良好的线性和口间隔离性能。测试结果显示，在固定中频160MHz，本振输入功率0dBm条件下，在3．5～5GI-IzRF频带内，最小变频损耗为8．3dB，1dB压缩点功率为8．0dBm，LO至Ⅲ之问的隔离度为38dB。

基于三导体耦合线的毫米波Marchand balun建模与设计（英文）

提出了一种基于三导体耦合线结构的毫米波Marchand巴伦的新型宽带模型.基于c模和π模理论,对三导体耦合线进行了分析并采用传输线和理想变压器对其建立了模型.通过电磁场仿真提取了模型参数并使用该耦合线模型建立了Marchand巴伦的模型.基于该模型,使用GaAs工艺设计了一种毫米波Marchand巴伦并进行了流片制造,所设计的巴伦工作在15~55 GHz频率范围,测试结果表明该巴伦具有较好的幅值和相位平衡度,同时验证了模型的准确性.

Delay and Energy Efficient Design of an On-Chip Bus with Repeaters Using a New Spatial and Temporal Encoding Technique

On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.

Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

LTCC小型化Balun设计

介绍了一种基于LTCC(低温共烧陶瓷)技术的小型化balun的设计。设计的Balun采用Marchand balun结构,使用LTCC技术实现多层结构、上下耦合的方式减小balun的体积并拓展带宽。该balun工作在1.7～2.2GHz,体积为2.8mm×3mm×1mm,并且平衡端口输出具有良好的幅值平衡和180°相位差。

On-chip readout plasmonic mid-IR gas sensor

Gas identification and concentration measurements are important for both understanding and monitoring a variety of phenomena from industrial processes to environmental change.Here a novel mid-IR plasmonic gas sensor with on-chip direct readout is proposed based on unity integration of narrowband spectral response,localized field enhancement and thermal detection.A systematic investigation consisting of both optical and thermal simulations for gas sensing is presented for the first time in three sensing modes including refractive index sensing,absorption sensing and spectroscopy,respectively.It is found that a detection limit less than 100 ppm for CO2 could be realized by a combination of surface plasmon resonance enhancement and metal-organic framework gas enrichment with an enhancement factor over 8000 in an ultracompact optical interaction length of only several microns.Moreover,on-chip spectroscopy is demonstrated with the compressive sensing algorithm via a narrowband plasmonic sensor array.An array of 80 such sensors with an average resonance linewidth of 10 nm reconstructs the CO2 molecular absorption spectrum with the estimated resolution of approximately 0.01 nm far beyond the state-of-the-art spectrometer.The novel device design and analytical method are expected to provide a promising technique for extensive applications of distributed or portable mid-IR gas sensor.

Design Aspects of CMOS Compatible On-Chip Antenna for Applications of Contact-Less Smart Card

Design aspects of CMOS compatible on-chip antenna for applications of contact-less smart card are discussed.An on-chip antenna model is established and a design method is demonstrated.Experimental results show that system-on-chip integrating power reception together with other electronic functions of smart card applications is feasible.In a 6×10 -4T magnetic field of 22.5MHz,an on-chip power of 1.225mW for a 10kΩ load is obtained using a 4mm2 on-chip antenna.

Development of series SQUID array with on-chip filter for TES detector

A cold preamplifier based on superconducting quantum interference devices(SQUIDs)is currently the preferred readout technology for the low-noise transition edge sensor(TES).In this work,we have designed and fabricated a series SQUID array(SSA)amplifier for the TES detector readout circuit.In this SSA amplifier,each SQUID cell is composed of a first-order gradiometer formed using two equally large square washers,and an on-chip low pass filter(LPF)as a radiofrequency(RF)choke has been developed to reduce the Josephson oscillation interference between individual SQUID cells.In addition,a highly symmetric layout has been designed carefully to provide a fully consistent embedded electromagnetic environment and achieve coherent flux operation.The measured results show smooth V-Φcharacteristics and a swing voltage that increases linearly with increasing SQUID cell number N.A white flux noise level as low as 0.28μφ;/Hz;is achieved at 0.1 K,corresponding to a low current noise level of 7 pA/Hz;.We analyze the measured noise contribution at mK-scale temperatures and find that the dominant noise derives from a combination of the SSA intrinsic noise and the equivalent current noise of the room temperature electronics.

Novel Balun Structure for Dipole Antenna

A novel balun structure for dipole antenna,which is based on the current distribution on parallel microstrip lines and the emission cancellation characteristic of close equal and opposite currents,is proposed.The principle of the balun structure is first elaborated and verified.Then,a dipole antenna with resonance at 2.45 GHz is constructed using the balun and its radiation pattern is measured.The simulated and measured reflection coefficients(S_(11))of the antenna are in good agreement 2—3 GHz.The relative bandwidth with an S_(11) of below-10 dB is more than 25%.The antenna also shows a good radiation pattern at 2.45 GHz.The proposed structure can provide a new balun design method for dipole antennas.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

Planar Compact Dual-Band Coupled-Line Balun with High Isolation

A planar circuit structure, which is based on three cascaded pairs of coupled lines, an open stub, and an isolation resistor, is proposed in this paper to design a compact dual.band balun with high isolation. This circuit features equal power division with out of phase, all ports matching, high isolation between two outputs, compact structure, and inherent impedance transformation. The closedform design equations are derived based on the traditional transmission.line theory and even.(odd.) mode analysis. A practical dual.band balun, which operates at 0.9/1.8GHz, is designed and fabricated to validate the function of equal power division with out of phase and high isolation between two outputs. The consistency between the simulated and measured results verify the design theory.

A BALUN-BANDPASS FILTER WITH GOOD IN-BAND PERFORMANCE AND WIDE STOPBAND

A high performance Balun BandPass Filter (BPF) with capacitively loaded multiple coupled lines with very simple structure is proposed in this paper, this structure realizes simultaneous size reduction and superior harmonic response suppression performance in bandpass filtering meanwhile good differential performance of the Balun. The theory of this structure for unbalanced input into balanced output has been studied in this paper and a proper Balun and BPF characteristic by the symmetric feeding and skew symmetric feeding have been obtained to prove the theory. The enter frequency of the fabricated Balun-BPF is operated at 2.45 GHz with 6.93% Fractional Band Width (FBW), and this frequency is used for Bluetooth and some other communication systems. The differences between the two outputs are 180°± 1.92° in phase and within 0.33 dB in magnitude. At f0, the amplitude imbalance and phase difference are within 0.25 dB and 180.86°, respectively. The measured frequency responses agree well with the simulated ones. With the theoretical analyses and practical results, it is shown that the proposed one has the advantages of simple structure, convenient analysis and good performance of both BPF and Balun.

Measurements of Balun and Gap Effects in a Dipole Antenna

In the present paper, design and analysis of a 2.4 GHz printed dipole antenna for wireless communication applications are presented. Measurements on return loss and radiation pattern of this antenna configuration are included in this investigation. The printed dipole is combined with the feeding structure of a microstrip via-hole balun and is fabricated on an FR-4 printed-circuit-board substrate. Two inevitable discontinuities are introduced by this antenna architecture in the form of right-angle bends in the microstrip feed line and in the dipole’s gap, respectively. The impact of mitering these bends in the reflection coefficient, resonance bandwidth and radiation pattern of antenna has been investigated by means of simulation and experiment.

Comparative Analysis on Antenna Balun and Feeding Techniques of Step Constant Tapered Slot Antenna

This paper represents the performance analysis of the different shapes of antenna balun and feeding techniques for step constant tapered slot antenna. This work also addresses the benefits of antenna balun (circular and rectangular) along with two types of feeding techniques (Microstrip line L-shape and Microstrip line I-shape). The performance of the antenna for each technique is thoroughly investigated using Computer Simulation Technology (CST) Microwave Studio software simulation under the resonant frequency of 5.9 GHz. Results demonstrate that the proposed model is an effective tool for improving antenna performance. Moreover, an extensive comparison has been carried out between the two different shapes, with and without antenna balun and between two feeding techniques focusing on return losses, gain, directivity, and voltage standing wave ratio (VSWR).

Bandwidth-enhanced dual-polarized antenna with improved broadband integrated balun and distributed parasitic element

A bandwidth-enhanced dual-polarized antenna is proposed for 2/3/4/5G applications,which is composed of distributed parasitic elements(DPEs),a main radiator,two improved broadband integrated baluns and a reflector.First,a novel tooth-shape shorted slot line in the improved broadband integrated balun is analyzed to adjust the input impedance of the antenna.Then,DPEs with 2×2 circular plates loading over the main radiator are proposed to improve broadband impedance matching and radiation pattern.By utilizing impedance compensation of the tooth-shaped shorted slot line and the electromagnetic induction of the DPEs,the antenna achieves an enhanced impedance bandwidth and a stable radiation pattern.To verify these ideas,the bandwidth-enhanced dual-polarized antenna was fabricated and measured.The experimental results indicate that the proposed antenna achieves an operating bandwidth of 72.2%(1.69 to 3.60 GHz)with a return loss(RL)less than-15 dB and a port-to-port isolation(ISO)larger than 30 dB.The antenna obtains a half-power beamwidth(HPBW)within(66±5)°and a gain within(9.0±0.6)dBi in the 2/3/4G bands,and an HPBW within(61.5±2.5)°and a gain within(9.8±0.3)dBi in the 5G band.Across the whole band,the cross-polarization discrimination(XPD)and the front-to-back ratio are both larger than 20 dB.