A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-...A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.展开更多
Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative thr...Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.展开更多
本文对PD SOI NMOS器件进行了60Coγ射线总剂量辐照的实验测试,分析了不同的栅长对器件辐射效应的影响及其物理机理.研究结果表明,短沟道器件辐照后感生的界面态密度更大,使器件跨导出现退化.PD SOI器件的局部浮体效应是造成不同栅长器...本文对PD SOI NMOS器件进行了60Coγ射线总剂量辐照的实验测试,分析了不同的栅长对器件辐射效应的影响及其物理机理.研究结果表明,短沟道器件辐照后感生的界面态密度更大,使器件跨导出现退化.PD SOI器件的局部浮体效应是造成不同栅长器件辐照后输出特性变化不一致的主要原因.短沟道器件输出特性的击穿电压更低.在关态偏置条件下,由于背栅晶体管更严重的辐射效应,短沟道SOI器件的电离辐射效应比同样偏置条件下长沟道器件严重.展开更多
研究开发了0.4μm PD CMOS/SOI工艺,试制出采用H栅双边体引出的专用电路。对应用中如何克服PD SOI MOSFET器件的浮体效应进行了研究;探讨在抑制浮体效应的同时减少对芯片面积影响的途径,对H栅双边体引出改为单边体引出进行了实验研究。...研究开发了0.4μm PD CMOS/SOI工艺,试制出采用H栅双边体引出的专用电路。对应用中如何克服PD SOI MOSFET器件的浮体效应进行了研究;探讨在抑制浮体效应的同时减少对芯片面积影响的途径,对H栅双边体引出改为单边体引出进行了实验研究。对沟道长度为0.4μm、0.5μm、0.6μm、0.8μm的H栅PD SOI MOSFET单边体引出器件进行工艺加工及测试,总结出在现有工艺下适合单边体引出方式的MOSFET器件尺寸,并对引起短沟道PMOSFET漏电的因素进行了分析,提出了改善方法;对提高PD CMOS/SOI集成电路的设计密度和改进制造工艺具有一定的指导意义。展开更多
Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristic...Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristics and the breakdown voltage are studied in detail. Through simulations,it is found that the AC PD SOI device can suppress the floating effects and improve the breakdown characteristics over conventional partially depleted silicon-on-insulator devices. Also compared to the reported AC FD SOI device,the performance variation with device parameters is more predictable and operable in industrial applications. The AC FD SO1 device has thinner silicon film, which causes parasitical effects such as coupling effects between the front gate and the back gate and hot electron degradation effects.展开更多
通过模拟对ON、OFF、TG三种偏置下PD SOI NMOSFET的总剂量辐照效应进行了研究。模拟发现正沟道的最坏偏置是ON偏置,背沟道的最坏偏置与总剂量有关。当总剂量大时,背沟道的最坏偏置是OFF偏置;当总剂量小时则是TG偏置。而NMOSFET的最坏偏...通过模拟对ON、OFF、TG三种偏置下PD SOI NMOSFET的总剂量辐照效应进行了研究。模拟发现正沟道的最坏偏置是ON偏置,背沟道的最坏偏置与总剂量有关。当总剂量大时,背沟道的最坏偏置是OFF偏置;当总剂量小时则是TG偏置。而NMOSFET的最坏偏置则取决于起主要作用的是正栅还是背栅。由于辐照产生电子空穴对的过程与电场分布强相关,通过分析不同偏置下电场分布的差异确定最坏偏置的内在机制。展开更多
文摘A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.
基金Project supported by the Weapon Equipment Pre-Research Foundation of China(Grant No.9140A11020114ZK34147)the Shanghai Municipal Natural Science Foundation,China(Grant No.15ZR1447100)
文摘Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.
文摘本文对PD SOI NMOS器件进行了60Coγ射线总剂量辐照的实验测试,分析了不同的栅长对器件辐射效应的影响及其物理机理.研究结果表明,短沟道器件辐照后感生的界面态密度更大,使器件跨导出现退化.PD SOI器件的局部浮体效应是造成不同栅长器件辐照后输出特性变化不一致的主要原因.短沟道器件输出特性的击穿电压更低.在关态偏置条件下,由于背栅晶体管更严重的辐射效应,短沟道SOI器件的电离辐射效应比同样偏置条件下长沟道器件严重.
文摘研究开发了0.4μm PD CMOS/SOI工艺,试制出采用H栅双边体引出的专用电路。对应用中如何克服PD SOI MOSFET器件的浮体效应进行了研究;探讨在抑制浮体效应的同时减少对芯片面积影响的途径,对H栅双边体引出改为单边体引出进行了实验研究。对沟道长度为0.4μm、0.5μm、0.6μm、0.8μm的H栅PD SOI MOSFET单边体引出器件进行工艺加工及测试,总结出在现有工艺下适合单边体引出方式的MOSFET器件尺寸,并对引起短沟道PMOSFET漏电的因素进行了分析,提出了改善方法;对提高PD CMOS/SOI集成电路的设计密度和改进制造工艺具有一定的指导意义。
文摘Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristics and the breakdown voltage are studied in detail. Through simulations,it is found that the AC PD SOI device can suppress the floating effects and improve the breakdown characteristics over conventional partially depleted silicon-on-insulator devices. Also compared to the reported AC FD SOI device,the performance variation with device parameters is more predictable and operable in industrial applications. The AC FD SO1 device has thinner silicon film, which causes parasitical effects such as coupling effects between the front gate and the back gate and hot electron degradation effects.
文摘通过模拟对ON、OFF、TG三种偏置下PD SOI NMOSFET的总剂量辐照效应进行了研究。模拟发现正沟道的最坏偏置是ON偏置,背沟道的最坏偏置与总剂量有关。当总剂量大时,背沟道的最坏偏置是OFF偏置;当总剂量小时则是TG偏置。而NMOSFET的最坏偏置则取决于起主要作用的是正栅还是背栅。由于辐照产生电子空穴对的过程与电场分布强相关,通过分析不同偏置下电场分布的差异确定最坏偏置的内在机制。
