A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to t...A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.展开更多
Resistive switching random access memory(RRAM) is considered as one of the potential candidates for next-generation memory. However, obtaining an RRAM device with comprehensively excellent performance, such as high re...Resistive switching random access memory(RRAM) is considered as one of the potential candidates for next-generation memory. However, obtaining an RRAM device with comprehensively excellent performance, such as high retention and endurance, low variations, as well as CMOS compatibility, etc., is still an open question. In this work, we introduce an insert TaO_(x) layer into HfO_(x)-based RRAM to optimize the device performance. Attributing to robust filament formed in the TaO_(x) layer by a forming operation, the local-field and thermal enhanced effect and interface modulation has been implemented simultaneously. Consequently, the RRAM device features large windows(> 10^(3)), fast switching speed(-10 ns), steady retention(> 72h), high endurance(> 10^(8) cycles), and excellent uniformity of both cycle-to-cycle and device-to-device. These results indicate that inserting the TaO_(x) layer can significantly improve HfO_(x)-based device performance, providing a constructive approach for the practical application of RRAM.展开更多
A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the...A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.展开更多
A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective l...A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.展开更多
基金Project supported by the National Basic Research Program of China(Grant No.2015CB351906)the Science Foundation for Distinguished Young Scholars of Shaanxi Province,China(Grant No.2018JC-017)。
文摘A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.
基金supported by the National Key R&D Program of China under Grant No.2018YFA0701500the National Natural Science Foundation of China under Grant Nos.61825404,U20A20220,61732020,and 61851402+1 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDB44000000the China Postdoctoral Science Foundation under Grant No.2020M681167。
文摘Resistive switching random access memory(RRAM) is considered as one of the potential candidates for next-generation memory. However, obtaining an RRAM device with comprehensively excellent performance, such as high retention and endurance, low variations, as well as CMOS compatibility, etc., is still an open question. In this work, we introduce an insert TaO_(x) layer into HfO_(x)-based RRAM to optimize the device performance. Attributing to robust filament formed in the TaO_(x) layer by a forming operation, the local-field and thermal enhanced effect and interface modulation has been implemented simultaneously. Consequently, the RRAM device features large windows(> 10^(3)), fast switching speed(-10 ns), steady retention(> 72h), high endurance(> 10^(8) cycles), and excellent uniformity of both cycle-to-cycle and device-to-device. These results indicate that inserting the TaO_(x) layer can significantly improve HfO_(x)-based device performance, providing a constructive approach for the practical application of RRAM.
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No.2010ZX02201)the National Natural Science Foundation of China(No.61176069)the National Defense Pre-Research of China(No.51308020304)
文摘A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.
基金Project supported by the State Key Laboratory of Electronic Thin Films and Integrated Devices,UESTC(No.KFJJ201205)the Guangxi Department of Education(No.201202ZD041)+1 种基金the China Postdoctoral Science Foundation(Nos.2012M521127,2013T60566)the National Natural Science Foundation of China(Nos.61361011,61274077,61464003)
文摘A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.
