A new ultra-low specific on-resistance （Ron,sp） vertical double diffusion metal-oxide-semiconductor field-effect tran- sistor （VDMOS） with continuous electron accumulation （CEA） layer, denoted as CEA-VDMOS, is p...A new ultra-low specific on-resistance （Ron,sp） vertical double diffusion metal-oxide-semiconductor field-effect tran- sistor （VDMOS） with continuous electron accumulation （CEA） layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration （Am）. In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp. Especially, the two PNjunctions within the trench gate support a high gate--drain voltage in the off-state and on-state, re- spectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS （CSJ-VDMOS） at the same high breakdown voltage （BV）.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos.61176069 and 61376079)the Fundamental Research Funds for the Central Universities,China(Grant No.ZYGX2014Z006)
文摘A new ultra-low specific on-resistance （Ron,sp） vertical double diffusion metal-oxide-semiconductor field-effect tran- sistor （VDMOS） with continuous electron accumulation （CEA） layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration （Am）. In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp. Especially, the two PNjunctions within the trench gate support a high gate--drain voltage in the off-state and on-state, re- spectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS （CSJ-VDMOS） at the same high breakdown voltage （BV）.
