Iterative Decoding of Parallel Concatenated Block Codes and Coset Based MAP Decoding Algorithm for F24 Code

A multi dimensional concatenation scheme for block codes is introduced, in which information symbols are interleaved and re encoded for more than once. It provides a convenient platform to design high performance codes with flexible interleaver size. Coset based MAP soft in/soft out decoding algorithms are presented for the F24 code. Simulation results show that the proposed coding scheme can achieve high coding gain with flexible interleaver length and very low decoding complexity.

Using Pipeline Instructions by Parallel Simulation of Mathematical Models

Simulation is an important and useful technique helping users understand and model real life systems. Once built, the models can run proving realistic results. This supports making decisions on a more logical and scientific basis. The paper introduces method of simulation, and describes various types of its application. The authors used the method of analysis of the creation and implementation of the programme code. The authors compared parallel instruction of computing defined to pipelined instructions. The power of simulation is that a common model can be used to design a large variety of systems. An important aspect of the simulation method is that a simulation model is designed to be repeated in actual computer systems, especially in multicore processors. For this reason, it is important to minimize average waiting time for fetch and decode stage instructions. The objective of the research is to prove that the parallel operation of programme code is faster than sequential operation code on the multi processor architecture. The system modeling uses methods and simulation on the parallel computer systems is very precise. The time benefit gained in simulation of mathematical model on the pipeline processor is higher than the one in simulation of mathematical model on the multi processors computer system.

Secure Transmission Scheme for Parallel Relay Channels Based on Polar Coding

This paper considers the use of polar codes to enable secure transmission over parallel relay channels.By exploiting the properties of polar codes over parallel channels, a polar encoding algorithm is designed based on Channel State Information（CSI） between the legitimate transmitter（Alice） and the legitimate receiver（Bob）.Different from existing secure transmission schemes, the proposed scheme does not require CSI between Alice and the eavesdropper（Eve）. The proposed scheme is proven to be reliable and shown to be capable of transmitting information securely under Amplify-and-Forward（AF） relay protocol, thereby providing security against passive and active attackers.

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

Ferroelectric Liquid Crystal Gates and Optical Computing

The surface stabilized ferroelectric liquid crystal device configuration and ferroelectric liquid crystal gates are described.The liquid crystal electrooptical gates have numerous applications,including optical computation,optodigital circuits,and optical communication networks.

Multiple accumulated-crossover parallel concatenated SPC codes

By constructing an accumulated-crossover relationship in multiple parallel concatenated single parity check （M-PC-SPC） codes, a class of error-correcting codes, termed multiple accumulated-crossover parallel concatenated single parity check （M-ACPC-SPC） codes, is proposed. M-ACPC-SPC codes possess linear encoding complexity and can be decoded iteratively with low complexity by the sum-product algorithm （SPA）. Simulation results show that M-ACPC-SPC codes have lower error floors than M-PCSPC codes with the same dimension, and when the dimension is 5, M-ACPC-SPC codes achieve bit error rate （BER） better than （3, 6） regular low density parity check （LDPC） codes.

A novel satellite-equipped receiver for autonomous monitoring of GNSS navigation signal quality

Global navigation satellite system(GNSS) comes with potential unavoidable application risks such as the sudden distortion or failure of navigation signals because its satellites are generally operated until failure. In order to solve the problems associated with these risks, receiver autonomous integrity monitoring(RAIM) and ground-based signal quality monitoring stations are widely used. Although these technologies can protect the user from the risks, they are expensive and have limited region coverage. Autonomous monitoring of satellite signal quality is an effective method to eliminate these shortcomings of the RAIM and ground-based signal quality monitoring stations; thus, a new navigation signal quality monitoring receiver which can be equipped on the satellite platform of GNSS is proposed in this paper. Because this satellite-equipped receiver is tightly coupled with navigation payload, the system architecture and its preliminary design procedure are first introduced. In theory, code-tracking loop is able to provide accurate time delay estimation of received signals. However, because of the nonlinear characteristics of the navigation payload, the traditional code-tracking loop introduces errors. To eliminate these errors, the dummy massive parallel correlators(DMPC) technique is proposed. This technique can reconstruct the cross correlation function of a navigation signal with a high code phase resolution. Combining the DMPC and direct radio frequency(RF) sampling technology, the satellite-equipped receiver can calibrate the differential code bias(DCB) accurately. In the meantime, the abnormities and failures of navigation signal can also be monitored. Finally, the accuracy of DCB calibration and the performance of fault monitoring have been verified by practical test data and numerical simulation data, respectively. The results show that the accuracy of DCB calibration is less than 0.1 ns and the novel satellite-equipped receiver can monitor the signal quality effectively.