Accelerated generation of holograms with ultra-low memory symmetrically high-compressed look-up table

Computer-generated holography technology has been widely applied,and as research in this field deepens,the demand for memory and computational power in small AR and VR devices continues to increase.This paper presents a hologram generation method,i.e.,a symmetrically high-compressed look-up table method,which can reduce memory usage by50%.In offline computing,half of the basic horizontal and vertical modulation factors are stored,halving the memory requirements without affecting inline speed.Currently,its potential extends to various holographic applications,including the production of optical diffraction elements.

A general purpose exact Rayleigh scattering look-up table for ocean color remote sensing

The current exact Rayleigh scattering calculation of ocean color remote sensing uses the look-up table （LUT）, which is usually created for a special remote sensor and cannot be applied to other sensors. For practical application, a general purpose Rayleigh scattering LUT which can be applied to all ocean color remote sensors is generated. An adding-doubling method to solve the vector radiative transfer equation in the plane-parallel atmosphere is deduced in detail. Compared with the exact Rayleigh scattering radiance derived from the MODIS exact Rayleigh scattering LUT, it is proved that the relative error of Rayleigh scattering calculation with the adding-doubling method is less than 0.25%, which meets the required accuracy of the atmospheric correction of ocean color remote sensing. Therefore, the adding-doubling method can be used to generate the exact Rayleigh scattering LUT for the ocean color remote sensors. Finally, the general purpose exact Rayleigh scattering LUT is generated using the adding-doubling method. On the basis of the general purpose LUT, the calculated Rayleigh scattering radiance is tested by comparing with the LUTs ofMODIS, SeaWiFS and the other ocean color sensors, showing that the relative errors are all less than 0.5%, and this general purpose LUT can be applied to all ocean color remote sensors.

Fine Doppler shift acquisition algorithm for BeiDou software receiver by a look-up table

The BeiDou software receiver uses the fast Fourier transform(FFT)to perform the acquisition.The Doppler shift estimation accuracy should be less than 500 Hz to ensure satellite signals to enter a locked state in the tracking loop.Since the frequency step is usually 500 Hz or larger,the Doppler shift estimation accuracy cannot guarantee that satellite signals are brought into a stable tracking state.The straightforward solutions consist in increasing the sampling time and using zero-padding to improve the frequency resolution of the FFT.However,these solutions intensify the complexity and amount of computation.The contradiction between the acquisition accuracy and the computational load leads us to research for a more simple and effective algorithm,which achieves fine acquisition by a look-up table.After coarse acquisition using the parallel frequency acquisition(PFA)algorithm,the proposed algorithm optimizes the Doppler shift estimation through the look-up table method based on the FFT results to improve the acquisition accuracy of the Doppler shift with a minimal additional computing load.When the Doppler shift is within the queryable range of the table,the proposed algorithm can improve the Doppler shift estimation accuracy to 50 Hz for the BeiDou B1I signal.

Performance of global look-up table strategy in digital image correlation with cubic B-spline interpolation and bicubic interpolation

Global look-up table strategy proposed recently has been proven to be an efficient method to accelerate the interpolation, which is the most time-consuming part in the iterative sub-pixel digital image correlation （DIC） algorithms. In this paper, a global look-up table strategy with cubic B-spline interpolation is developed for the DIC method based on the inverse compositional Gauss-Newton （IC-GN） algorithm. The performance of this strategy, including accuracy, precision, and computation efficiency, is evaluated through a theoretical and experimental study, using the one with widely employed bicubic interpolation as a benchmark. The global look-up table strategy with cubic B-spline interpolation improves significantly the accuracy of the IC-GN algorithm-based DIC method compared with the one using the bicubic interpolation, at a trivial price of computation efficiency.

Research of NO_(2) vertical profiles with look-up table method based on MAX-DOAS

Obtaining the vertical distribution profile of trace gas is of great significance for studying the diffusion procedure of air pollution.In this article,a look-up table method based on multi-axis differential optical absorption spectroscopy(MAX-DOAS)technology is established for retrieving the tropospheric NO_(2) vertical distribution profiles.This method retrieves the aerosol extinction profiles with minimum cost function.Then,the aerosol extinction profiles and the atmospheric radiation transfer model(RTM)are employed to establish the look-up table for retrieving the NO_(2) vertical column densities(VCDs)and profiles.The measured NO_(2) differential slant column densities(DSCDs)are compared with the NO_(2) DSCDs simulated by the atmospheric RTM,and the NO_(2) VCDs,the weight factor of NO_(2) in the boundary layer,and the boundary layer height are obtained by the minimization process.The look-up table is established to retrieve NO_(2) VCDs based on MAX-DOAS measurements in Huaibei area,and the results are compared with the data from Copernicus Atmospheric Monitoring Service(CAMS)model.It is found that there are nearly consistent and the correlation coefficient R2 is more than 0.86.The results show that this technology provides a more convenient and accurate retrieval method for the stereoscopic monitoring of atmospheric environment.

WinoNet:Reconfigurable look-up table-based Winograd accelerator for arbitrary precision convolutional neural network inference

To solve the hardware deployment problem caused by the vast demanding computational complexity of convolutional layers and limited hardware resources for the hardware network inference,a look-up table(LUT)-based convolution architecture built on a field-programmable gate array using integer multipliers and addition trees is used.With the help of the Winograd algorithm,the optimization of convolution and multiplication is realized to reduce the computational complexity.The LUT-based operator is further optimized to construct a processing unit(PE).Simultaneously optimized storage streams improve memory access efficiency and solve bandwidth constraints.The data toggle rate is reduced to optimize power consumption.The experimental results show that the use of the Winograd algorithm to build basic processing units can significantly reduce the number of multipliers and achieve hardware deployment acceleration,while the time-division multiplexing of processing units improves resource utilization.Under this experimental condition,compared with the traditional convolution method,the architecture optimizes computing resources by 2.25 times and improves the peak throughput by 19.3 times.The LUT-based Winograd accelerator can effectively solve the deployment problem caused by limited hardware resources.

Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach

This brief proposes an area and speed efficient implementation of symmetric finite impulse response (FIR) digital filter using reduced parallel look-up table (LUT) distributed arithmetic (DA) based approach. The complexity lying in the realization of FIR filter is dominated by the multiplier structure. This complexity grows further with filter order, which results in increased area, power, and reduced speed of operation. The speed of operation is improved over multiply-accumulate approach using multiplier less conventional DA based design and decomposed DA based design. Both the structure requires B clock cycles to get the filter output for the input width of B, which limits the speed of DA structure. This limitation is addressed using parallel LUTs, called high speed DA FIR, at the expense of additional hardware cost. With large number of taps, the number of LUTs and its size also becomes large. In the proposed method, by exploiting coefficient symmetry property, the number of LUTs in the decomposed DA form is reduced by a factor of about 2. This proposed approach is applied in high speed DA based FIR design, to obtain area and speed efficient structure. The proposed design offers around 40% less area and 53.98% less slice-delay product (SDP) than the high throughput DA based structure when it’s implemented over Xilinx Virtex-5 FPGA device-XC5VSX95T-1FF1136 for 16-tap symmetric FIR filter. The proposed design on the same FPGA device, supports up to 607 MHz input sampling frequency, and offers 60.5% more speed and 67.71% less SDP than the systolic DA based design.

The establishment of crystal position look-up table for positron emission tomography with block detectors

A method has been developed to establish the crystal position look-up table for positron emission tomography with block detectors. It is based on the principle that the counts in crystal position histogram obey the Gaussian mixture model (GMM). This method has taken full consideration of the characteristics of the GMM and the detector itself. The experimental results have proved that it is simple, reliable, and universal.

CRC Look-up Table Optimization for Single-Bit Error Correction

Many communication systems use the cyclic redundancy code （CRC） technique for protecting key data fields from transmission errors by enabling both single-bit error correction and multi-bit error detection. The look-up table design is very important for the error-correction implementation. This paper presents a CRC look-up table optimization method for single-bit error correction. The optimization method minimizes the address length of the pre-designed look-up table while satisfying certain restrictions. The circuit implementation is also presented to show the feasibility of the method in the application specific integrated circuit design. An application of the optimization method in the generic framing procedure protocol is implemented using field programmable gatearrays. The result shows that the memory address length has been minimized, while keeping a very simple circuit implementation.

Differential Spatial Modulation Mapping Algorithms

Differential spatial modulation(DSM)is a multiple-input multiple-output(MIMO)transmission scheme.It has attracted extensive research interest due to its ability to transmit additional data without increasing any radio frequency chain.In this paper,DSM is investigated using two mapping algorithms:Look-Up Table Order(LUTO)and Permutation Method(PM).Then,the bit error rate(BER)performance and complexity of the two mapping algorithms in various antennas and modulation methods are verified by simulation experiments.The results show that PM has a lower BER than the LUTO mapping algorithm,and the latter has lower complexity than the former.

MADET-A Machine-Description Table Based Instruction Scheduler in TH-RISC for Exploiting Instruction Level Parallelism

This paper presents a parameterized instruction scheduling algorithm based on machine description table for TH-RISC system, having a (3-5) stages pipeline structure.It would provide considerable fiexibility for instruction scheduling, improving execution efficiency for rapidly upgrading RISC machines. Alld, using this instruction scheduler as a tool, the effect of several methods for solving instruction interlock problem has been analyzed. Finally, a high performance approach combining the hardware feasibility and software effectiveness for solving instruction interlock problem, the improvement of instruction level parallelism (ILP) and speed-up results are given.The algorithm complexity is O(n2).

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table （LUT） approach. Circuit simu- lation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in ca- dence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the perform- ance of circuits implemented using 14 nm nMOSFET.

Accurate and fast table look-up models for leakage current analysis in 65nm CMOS technology

Novel physical models for leakage current analysis in 65 nm technology are proposed. Taking into consideration the process variations and emerging effects in nano-scaled technology, the presented models are capable of accurately estimating the subthreshold leakage current and junction tunneling leakage current in 65 nm technology. Based on the physical models, new table look-up models are developed and first applied to leakage current analysis in pursuit of higher simulation speed. Simulation results show that the novel physical models are in excellent agreement with the data measured from the foundry in the 65 nm process, and the proposed table look-up models can provide great computational efficiency by using suitable interpolation techniques. Compared with the traditional physical-based models, the table look-up models can achieve 2.5X speedup on average on a variety of industry circuits.

基于PZT的微驱动定位系统及控制方法的研究

介绍了基于PZT驱动的一维微动工作台。该微动台采用柔性平行板铰链机构,对其进行了出力和位移关系的分析,并且进行了ANSYS的有限元分析设计,求得了系统的固有频率和最大位移。其理论分析、有限元计算和试验测试结果的对比分析的一致性说明了理论分析的正确性和数值分析的可靠性。使用精密光栅进行微位移闭环检测,使用哈工大博实精密测控公司研制的压电陶瓷驱动电源。采用单神经元自适应PID控制算法对系统进行控制,单神经元具有自学习和自适应能力,而且结构简单易于计算;而传统的PID调节器也具有结构简单、调整方便和参数整定与工程指标联系密切等特点。推导了单神经元自适应PID控制器,并进行了实验,微位移为20μm时的响应时间为12ms,实验证明了该方法的有效性。

CRC查询表及其并行矩阵生成方法

循环冗余校验码(CRC)被广泛应用于通信领域。直接按位计算CRC校验值的方法难以满足高速链路要求,查询表方法与并行处理在很大程度上可以突破处理速度上的瓶颈。对查询表与并行处理矩阵之间的关系进行探讨,给出任意阶次生成多项式及任意处理位宽的查询表并行矩阵生成方法,并衍生出块处理方法。对表查询方法、并行矩阵查询方法及块处理方法的性能进行了比较分析,结果表明,并行处理位宽w增加,处理时间减少,并行矩阵方法在存储空间上表现更优;块处理通过减小校验序列长度,运算速度显著提高。

逆变器并联系统的新功率算法及实现

针对数字域下传统功率计算的积分延时影响并联系统的稳定性和动态性能的问题,提出一种无积分单元的功率计算方法。该方法根据正弦信号的三要素复原信号的原理,复现电压电流信号,仅用前后两拍的数值就可以实时计算平均功率。且在负载突变后,仅需一个采样周期即可得到平均功率真实值,动态跟踪好。减小了计算延时,提高了并联系统的稳定性和动态性能,因抛弃了正余弦表,占用DSP资源少,计算量小。仿真和理论计算对比表明该方法稳态误差小于0.04%和负载突变的动态响应快。两台75kVA/50Hz的单相逆变器并联实验验证了该方法的有效性。

基于固态硬盘内部并行的数据库表扫描与聚集

随着基于闪存的固态硬盘在个人计算机和企业服务器上的广泛应用,固态硬盘受到学术界和工业界越来越多的关注.除了具有闪存存储器的优良特性之外,固态硬盘内部还具有丰富的并行特性.传统数据库系统的物理操作表扫描和上层聚集操作是针对磁盘的机械特性和对称读写特性而设计的,并不能发挥固态硬盘内部并行特性的优势.文中首先将固态硬盘作为一个黑盒进行探测以了解其内部的并行特性.在此基础上,对传统数据库表扫描操作进行相应的改进,提出一种并行表扫描模型ParaSSDScan以充分利用固态硬盘内部丰富的并行特性.其次,基于并行表扫描模型,文中还提出一种高效的并行聚集操作模型ParaSSDAggr,并利用该聚集操作模型实现几种常见聚集操作.最后,通过实验表明并行表扫描和并行聚集操作的性能较之传统数据库表扫描和聚集操作的性能分别提高了3倍和4倍,同时实验结果还表明并行聚集操作对内存的需求不大.并行表扫描和并行聚集操作大大提高了表扫描和聚集操作的性能,充分说明了固态硬盘内部并行特性的优越性.

提高数据仓库中查询性能的一种并行多表连接算法

星型模式是当前数据仓库设计中广泛采用的逻辑模式。针对星型模式数据仓库中潜在的查询性能问题，结合数据仓库中的ORV，利用面向对象中的消息机制，提出了基于对象关系视图（ORV）的多表连接并行查询算法，并对算法的磁盘I/O操作次数、算法的时间复杂度进行了分析。

JESD204B接口协议中的8B10B编码器设计

基于JESD204B接口协议设计和实现了一种新型8B10B编码器。利用极性信息简化编码码表;利用3B4B与5B6B并行编码提升电路工作频率;利用人为加入一位均衡信息,减少逻辑处理层数。仿真结果表明,电路单元面积1 756 mm2、功耗1.13 m W及最大工作频率342 m Hz,相较于传统方法具有一定的改进且完全符合JESD204B协议规范。可应用于基于JESD204B接口协议的高速串行接口的设计中。

PaSeM:并行无冲突的网络流量会话管理

网络会话管理是网络流量监控、状态防火墙、入侵防御、网络地址转换、负载分流等网络在线业务的关键共性技术,对于准确、快速、灵活地跟踪、分析和处置网络流量中的协议交互过程、端对端行为和通信内容起着基础性支撑作用.近年来,随着P2P(Peer-to-Peer)、VoIP(Voiceover IP)、网络流媒体等新兴应用的快速发展,网络流量和会话呈现爆炸式增长,如何实现高效的会话管理成为人们面临的一项挑战.文中提出了一种适用于并行执行环境的网络会话管理方案PaSeM(Parallel Session Management),采用基于散列表的无锁会话表设计和多种并行策略,讨论并解决了在高速网络环境下面临的各种并行冲突问题,给出了会话表查询和动态管理的高效并行算法,实现了对报文和会话的并行无冲突的高效处理.基于G/G2/n1排队模型和空竭服务多重休假M/G+D/1排队模型对PaSeM的性能进行了理论分析,对于稳态下并行处理单元(PE)数量、任务队列长度、存储开销与报文到达速率、会话到达速率之间的关系以及其它关键参数应满足的条件给出了定量计算方法.最后,采用基于IXP2400网络处理器的硬件平台进行了原型开发和实验.实验结果表明,PaSeM对于会话管理和报文处理具有较好的并行加速效果,理论计算值与实验值能较好地吻合,报文处理的并行效率均值接近1,当会话管理单元个数为4时,会话处理并行效率为65.4%(亦即加速比为2.62),当会话管理单元个数为8时,会话处理并行效率仍然达到了48.3%(加速比为3.86),能够满足当前高速网络环境流量处理的性能要求;在最大吞吐量负载下队列长度及其变化幅度都处于合理范围,会话表垃圾比率维持在较低的水平上(实验结果为小于9%),与已有的工作相比为优.