Principle and Implementation of an MC4044-Based Phase Locked Loop for Constant Speed Control

An inexpensive MC4044-based phase locked loop for constant speed control of a DC motor is discussed. It operates on a principle similar to that of a frequency synthesizer. The paper introduces the system configuration with a detailed description of its operating principle, some practical design considerations are discussed with an experimental study to test the control performance of the newly designed system. The experimental result shows that the phase locked control system can regulate the speed of a DC torque motor with a precision up to 0.0022%(1).[

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

THE DESIGN OF AN ALL-DIGITAL PHASE-LOCKED LOOP WITH LOW JITTER BASED ON ISF ANALYSIS

A low jitter All-Digital Phase-Locked Loop （ADPLL） used as a clock generator is designed. The Digital-Controlled Oscillator （DCO） for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable. Based on the Impulse Sensitivity Function （ISF） analysis, an effective way is proposed to reduce the ADPLL＇s jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one. The ADPLL is implemented in a 0.18μm CMOS process with 1.SV supply voltage, occupies 0.046mm^2 of on-chip area. According to the measured results, the ADPLL can operate from 108MHz to 304MHz, and the peak-to-peak jitter is 139ps when the DCO＇s output frequency is 188MHz.

Low phase noise millimeter wave monolithic integrated phase locked-loop

A Monolithic integrated phase locked-loop （PLL） with a low phase noise is proposed in this paper. Several techniques are utilized to improve the performance of the PLL which works at the milli- meter-wave band. The on-chip high-Q eoplanar waveguides （CPWs） are utilized in the resonant tank and the differential current amplifier with a resonator is used to realize the VCO. In the output buffer circuit, several stages of cascaded source-followers connect and differential amplifiers are adopted to improve the driving capability of the PLL＇ s output signals. An improved analog multiplier topology is also used in the PD circuit to improve the gain of the PD. The proposed PLL is realized with a 0.2p, m GaAs pseudomorphie high electron mobility transistor （PHEMT） process. At 10 kHz offset from the center frequency, the measured output phase noise of the PLL output is only -88.83dBc/Hz. The circuit exhibits a low root mean sauare （RMS） litter of 1.68Ds.

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

PLL DEMODULATION TECHNIQUE FOR M-RAY POSITION PHASE SHIFT KEYING

The paper presents a kind of transmission system which employs M-ary Position Phase Shift Keying(MPPSK) to send data and Phase Locked Loop(PLL) based techniques for data retrieve.With a single PLL, MPPSK demodulation is achieved, as well as carrier recovery and symbol synchronization.Firstly, MPPSK modulation method is briefly introduced.2PPSK's PSD expression is given with its optimization result.Orthogonal Phase Detector(PD) and static threshold are used for the purpose of wider phase range and simplicity in demodulation.The data rate is alterable, which is 4.65 kbps for 2PPSK and 9.3 kbps for 4PPSK in the paper.Then some indicative comparisons in Signal to Noise Ratio Symbol Error Rate(SNR-SER) are made among 2PPSK, 3PPSK and 4PPSK, of which 4PPSK has proved to be optimal in ten slots each symbol conditions.And finally, it is demonstrated by system simulations that lower than 10-4 Symbol Error Rate(SER) performance can be obtained at 13 dB symbol SNR.

A novel Doppler frequency measurement method based on the closed-loop signal correlation for deep space exploration

In deep space exploration,it is necessary to improve the accuracy of frequency measurement to meet the requirements of precise orbit determination and various scientific studies.A phase detector is one of the key modules that restricts the tracking performance of phase-locked loop(PLL).Based on the phase relationship between adjacent signals in the time domain,a novel phase detector is presented to replace the arctangent phase detector.The new PLL,which is a closed loop signal correlation algorithm,shows good performance in tracking signals with high precision and the tracking accuracy of frequency of1 second integration is close to Cramer-Rao lower bound(CRLB)when setting proper parameters.Actual data processing results further illustrate the excellent performance of the novel PLL.

Control of Z-Source Inverter Connected to a Single-Phase AC Utility System

This paper presents a single-phase Z-source inverter as a power conditioning system for a single phase utility connected system. Z-source inverter is a single-stage topology that has buck-boost feature, which is possible because of additional shoot through state introduced in zero state of the conventional inverter pulse width modulation and provides desired output AC voltage. Small distributed generation （DG） system with alternate energy sources requires power conditioning units with low cost, high efficiency and tolerance to wide range of input voltage variation and has to perform various functions such as dc-ac conversion, system control and achieve power quality norms. To meet some of these requirements a two-loop control strategy for ac side control with grid current feedback with PI control and inner filter capacitor current feedback with proportional control and on dc side PID control for Z-source capacitor voltage regulation are employed, which gives good transient response also suppress load and source disturbances effectively. Theoretical analysis of proposed scheme is established and then simulation results are presented to validate proposed control strategy.

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

This work summarizes the structure and operating features of a high-performance 3-stage dual-delay-path (DDP) voltage-controlled ring oscillator (VCRO) with self-biased delay cells for Phase-Locked Loop (PLL) structurebased clock generation and digital system driving. For a voltage supply VDD = 1.8 V, the resulting set of performance parameters include power consumption PDC = 4.68 mW and phase noise PN@1MHz = -107.8 dBc/Hz. From the trade-off involving PDC and PN, a system level high performance is obtained considering a reference figure-of-merit ( FoM = -224 dBc/Hz ). Implemented at schematic level by applying CMOS-based technology (UMC L180), the proposed VCRO was designed at Cadence environment and optimized at MunEDA WiCkeD tool.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

Current Mismatches in Charge Pumps of DLL-Based RF CMOS Oscillators

A research on the spurious tones due to the current mismatch in charge pumps of DLL(Delay Locked Loop) based RF CMOS oscillators is performed.An equation for strength evaluation of the spurious tones is derived.Two tables are provided to make it obvious to understand for the characteristics of spurious tones changing with related parameters.Some suggestions are given for the design of a DLL based RF CMOS oscillators.

A NEW CONTROL METHOD FOR ULTRASONIC MOTOR

A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference value than a zero one, the direction, in which the driving frequency of the motor should be shifted, can be promptly calculated. With the aid of a CPU and the phase locked frequency doubling technique, the motor can be steadily driven in a wide range of frequency and the optimum frequency can be captured rapidly and precisely. Experiment shows that the above method is available.

Joint frequency offset tracking and PAPR reduction algorithm in OFDM systems

This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.

DPLL implementation in carrier acquisition and tracking for burst DS-CDMA receivers

This paper presents the architectures, algorithms, and implementation considerations of the digital phase locked loop (DPLL) used for burst-mode packet DS-CDMA receivers. As we know, carrier offset is a rather challenging problem in CDMA system. According to different applications, different DPLL forms should be adopted to correct different maximum carrier offset in CDMA systems. One classical DPLL and two novel DPLL forms are discussed in the paper. The acquisition range of carrier offset can be widened by using the two novel DPLL forms without any performance degradation such as longer acquisition time or larger variance of the phase error. The maximum acquisition range is 1/(4T), where T is the symbol period. The design can be implemented by FPGA directly.

Stable multi-frequency generator based on phase-locked optical frequency combs

A photonic generation of multi-frequency source based on the heterodyne of two phase-locked optical frequency combs（OFCs） is proposed and demonstrated.By applying an optical phase-locked loop,the phase noise induced by optical links is decreased by approximately 70,66,and 35 dB at 0.01,0.1,and 1.0 Hz offset frequencies,respectively.The proposed scheme provides 8 radio frequency signals,the frequencies of which span from 540 to 4040 MHz,with a 500-MHz interval.The number of generated signals can be readily scaled by using OFCs with broader bands,whereas the frequencies can be scaled by tuning the repetition rates of OFCs.

A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .

Non-PLL high-precision synchronous sampling method among lots of acoustics acquisition channels for underwater multilinear array seismic exploration system

Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.