In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LA...In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.展开更多
This paper signifies the study of modeling and simulation of a single phase matrix converter for induction heating system. The working principle and the control method, using PID are revealing in detail. The performan...This paper signifies the study of modeling and simulation of a single phase matrix converter for induction heating system. The working principle and the control method, using PID are revealing in detail. The performance of the system is carried out in MATLAB/Simulink environment with pulse width modulation switching strategy by varying the duty cycle. PID control is employed to obtain the better performance for a specified input supply for various output frequencies. The proposed control strategy of AC to AC converter has been discussed with a wide range of operating frequencies and results in low Total Harmonic Distortion.展开更多
This paper discusses a novel boost single-phase active AC-DC converters, named low-end semi-controlled bridge AC-DC converter. By analysis, its topology and principle can be derived from the conventional single-phase ...This paper discusses a novel boost single-phase active AC-DC converters, named low-end semi-controlled bridge AC-DC converter. By analysis, its topology and principle can be derived from the conventional single-phase power factor corrector （ PFC）. But it has also some differences, such as power device positions, inductor type, input voltage waveform detection and induction current detection, so its design is also different. The converter is implemented by employing two current detection approaches, i.e., current transformer detection and shunt resistor detection. Consequently, it can provide a steady DC output voltage with a low voltage ripple, approximately unitary input power factor and 2.5 kW output power. The experimental results show validity of the theoretical analysis.展开更多
Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
In this paper,to study the power loss of converter for elevator,The analysis is to establish relationship between parameters(current,voltages and losses in the inverter and converter) relevant for sizing of major comp...In this paper,to study the power loss of converter for elevator,The analysis is to establish relationship between parameters(current,voltages and losses in the inverter and converter) relevant for sizing of major components of the drive was done.) For high PWM(pulse width modulation) frequency like in elevator applications of fpwm =10kHz,switching losses are dominant and are about 2/3 of the total losses on IGBT switch.Transition from continuous 3 phase to discontinuous 2 phase PWM results in 50% reduction of switching loses on IGBT devices providing that PWM is not done over 60deg angle in a particular phase when current has maximum value.Total losses on IGBT(conduction + switching) are reduced approximately by ～1/3 what is still a significant reduction.Two phase PWM with reduced losses can be used for applications when acoustic noise due to increased current ripple is not significant and fall back solution to regular 3 phase PWM when drive operates under rare extreme conditions resulting in increased heat sink temperature.The analysis will be examined by further laboratory testing simulating 60% duty cycle on a dynamometer.展开更多
基于移相加占空比控制策略的三有源桥TAB(triple active bridge)DC-DC变换器具有效率高和软开关范围可扩展等优点,但其小信号建模过程复杂、闭环控制环路参数整定困难。针对该问题,提出1种TAB工作在移相加占空比控制下的全阶连续广义状...基于移相加占空比控制策略的三有源桥TAB(triple active bridge)DC-DC变换器具有效率高和软开关范围可扩展等优点,但其小信号建模过程复杂、闭环控制环路参数整定困难。针对该问题,提出1种TAB工作在移相加占空比控制下的全阶连续广义状态平均建模和PI控制器设计方法。首先,分析TAB的运行原理和Y型等效结构;然后,结合移相加占空比控制的特点和交流方波源等效方法,推导出TAB的广义状态空间平均模型;接着,在推得模型的基础上求得输入到输出的传递函数,设计出PI控制器参数。最后,结合数字仿真及样机实验验证了所提方法的正确性及有效性。展开更多
为解决双向DC-DC变换器(dual active bridge,DAB)采用单移相(single-phase-shift,SPS)控制产生的回流功率较高及动态性能较差的问题,提出一种采用双重移相(dual-phase-shift,DPS)控制下的最小回流功率算法与直接功率控制相结合的方法。...为解决双向DC-DC变换器(dual active bridge,DAB)采用单移相(single-phase-shift,SPS)控制产生的回流功率较高及动态性能较差的问题,提出一种采用双重移相(dual-phase-shift,DPS)控制下的最小回流功率算法与直接功率控制相结合的方法。首先对DPS控制下的基本原理及回流功率特性进行分析,并建立回流功率与移相比之间的数学关系,从而推导出各分段条件下回流功率在各阶段最小化的方案。其次在保证对变换器回流功率最小化的同时提出结合直接功率法来显著提高变换器的动态性能。最后通过MATLAB/Simulink中建立的仿真验证了上述控制策略的有效性。展开更多
基金Supported by National Natural Science Foundation of China (No. 10405023)Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)
文摘In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.
文摘This paper signifies the study of modeling and simulation of a single phase matrix converter for induction heating system. The working principle and the control method, using PID are revealing in detail. The performance of the system is carried out in MATLAB/Simulink environment with pulse width modulation switching strategy by varying the duty cycle. PID control is employed to obtain the better performance for a specified input supply for various output frequencies. The proposed control strategy of AC to AC converter has been discussed with a wide range of operating frequencies and results in low Total Harmonic Distortion.
文摘This paper discusses a novel boost single-phase active AC-DC converters, named low-end semi-controlled bridge AC-DC converter. By analysis, its topology and principle can be derived from the conventional single-phase power factor corrector （ PFC）. But it has also some differences, such as power device positions, inductor type, input voltage waveform detection and induction current detection, so its design is also different. The converter is implemented by employing two current detection approaches, i.e., current transformer detection and shunt resistor detection. Consequently, it can provide a steady DC output voltage with a low voltage ripple, approximately unitary input power factor and 2.5 kW output power. The experimental results show validity of the theoretical analysis.
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
文摘In this paper,to study the power loss of converter for elevator,The analysis is to establish relationship between parameters(current,voltages and losses in the inverter and converter) relevant for sizing of major components of the drive was done.) For high PWM(pulse width modulation) frequency like in elevator applications of fpwm =10kHz,switching losses are dominant and are about 2/3 of the total losses on IGBT switch.Transition from continuous 3 phase to discontinuous 2 phase PWM results in 50% reduction of switching loses on IGBT devices providing that PWM is not done over 60deg angle in a particular phase when current has maximum value.Total losses on IGBT(conduction + switching) are reduced approximately by ～1/3 what is still a significant reduction.Two phase PWM with reduced losses can be used for applications when acoustic noise due to increased current ripple is not significant and fall back solution to regular 3 phase PWM when drive operates under rare extreme conditions resulting in increased heat sink temperature.The analysis will be examined by further laboratory testing simulating 60% duty cycle on a dynamometer.
文摘基于移相加占空比控制策略的三有源桥TAB(triple active bridge)DC-DC变换器具有效率高和软开关范围可扩展等优点,但其小信号建模过程复杂、闭环控制环路参数整定困难。针对该问题,提出1种TAB工作在移相加占空比控制下的全阶连续广义状态平均建模和PI控制器设计方法。首先,分析TAB的运行原理和Y型等效结构;然后,结合移相加占空比控制的特点和交流方波源等效方法,推导出TAB的广义状态空间平均模型;接着,在推得模型的基础上求得输入到输出的传递函数,设计出PI控制器参数。最后,结合数字仿真及样机实验验证了所提方法的正确性及有效性。
文摘为解决双向DC-DC变换器(dual active bridge,DAB)采用单移相(single-phase-shift,SPS)控制产生的回流功率较高及动态性能较差的问题,提出一种采用双重移相(dual-phase-shift,DPS)控制下的最小回流功率算法与直接功率控制相结合的方法。首先对DPS控制下的基本原理及回流功率特性进行分析,并建立回流功率与移相比之间的数学关系,从而推导出各分段条件下回流功率在各阶段最小化的方案。其次在保证对变换器回流功率最小化的同时提出结合直接功率法来显著提高变换器的动态性能。最后通过MATLAB/Simulink中建立的仿真验证了上述控制策略的有效性。
