An all-optical phase detector by amplitude modulation of the local field in a Rydberg atom-based mixer

Recently,a Rydberg atom-based mixer was developed to measure the phase of a radio frequency(RF)field.The phase of the signal RF(SIG RF)field is down-converted directly to the phase of a beat signal created by the presence of a local RF(LO RF)field.In this study,we propose that the Rydberg atom-based mixer can be converted to an all-optical phase detector by amplitude modulation(AM)of the LO RF field;that is,the phase of the SIG RF field is related to both the amplitude and phase of the beat signal.When the AM frequency of the LO RF field is the same as the frequency of the beat signal,the beat signal will further interfere with the AM of the LO RF field inside the atom,and then the amplitude of the beat signal is related to the phase of the SIG RF field.The amplitude of the beat signal and the phase of the SIG RF field show a linear relationship within the range of 0 toπ/2 when the phase of the AM is set with a differenceπ/4 from the phase of the LO RF field.The minimum phase resolution can be as small as 0.6°by optimizing the experimental conditions according to a simple theoretical model.This study will expand and contribute to the development of RF measurement devices based on Rydberg atoms.

Design of Digital Multi-Radian Phase Detector on J-TEXT

A real time system used to detect phase difference between two sinusoidal signals is proposed in this paper. The system is designed to process the phase signal of the far-infrared （FIR） hydrogen cyanide （HCN） interferometer on J-TEXT. It is based on zero-crossing detection and makes use of the digital circuit. Compared with a traditional zero-crossing phase detector, it doesn＇t need to sacrifice the time resolution to expand the phase range. The phase difference is divided into two parts, the integer part and the fraction part. In each detecting cycle, they are detected separately. It outputs digital signals that are more stable for transmission. A prototype was built on J-TEXT using discrete components. A practical method is proposed to deal with the counting error caused by the deviation of electronic components in manufacture. Reasonable results were obtained on the prototype. The phase resolution reaches 2π/64 in test, and can still be improved by raising the clock frequency.

Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

A novel structure for a charge pump circuit is proposed, in which the charge-pump （CP） current can adaptively regulated according to phase-locked loops （PLL） frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0. 25μm 2. 5 V complementary metal-oxide-semiconductor （CMOS） mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector

The need for wide-band clock and data recovery （CDR） circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator （VCO）, a frequency detector, and a phase detector （FD＆PD） is described. A new automatic frequency band selection （FBS） without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility.

Self-Balanced Charge Pump with Fast Lock Circuit

A self-balanced charge pump （CP） with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25μm 1P5M complementary metal oxide semiconductor （CMOS） process with a 2.5 V supply voltage, HSPICE simulation shows that even if the mismatch of phase/frequency detector （PFD） was beyond 10%, the charge pump could still keep nearly zero phase error, Incorporated fast lock circuit can shorten start-up time to below 300 ns.

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer＇s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer＇s integrated phase noise is less than 1°（1 kHz to 100 MHz）with a 4.375 GHz carrier（after divide-by-2）,and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

fs-level laser–RF synchronization with a fiber-loop optical-microwave phase detector

In order to improve the precision of the laser–radio-frequency（RF） synchronization system from sub-picosecond to femtosecond（fs）, a synchronization system between a picosecond laser and a 1.3 GHz RF generator has been developed based on a fiber-loop optical-microwave phase detector（FLOM-PD）. Synchronization with fs-level（3.8 fs） rms jitter, integrated from 10 Hz to 1 MHz, is achieved for the first time, to the best of our knowledge, in this kind of configuration. This system will be used for the superconducting RF accelerator at Peking University.

Simulation of Analog Costas Loop Circuits

The analysis of stability and numerical simulation of Costas loop circuits for the high-frequency signals is a challenging task. The problem lies in the fact that it is necessary to observe very fast time scale of input signals and slow time scale of signal s phases simultaneously. To overcome this difficulty, it is possible to follow the classical ideas of Gardner and Viterbi to construct a mathematical model of Costas loop, in which only slow time change of signal s phases and frequencies is considered. Such an construction, in turn,requires the computation of phase detector characteristic, depending on the waveforms of the considered signals. In this paper, the problems of nonlinear analysis of Costas loops and the approaches to the simulation of the classical Costas loop, the quadrature phase shift keying(QPSK) Costas loop, and the two-phase Costas loop are discussed. The analytical method for the computation of phase detector characteristics of Costas loops is described.

Design of 25 Gbit/s half-rate CDR with 1:2 demultiplexer for 100 GbE optical interconnects

A 25 Gbit/s clock and data recovery （CDR） circuit with 1：2 demultiplexer for 100 Gbit/s Ethemet （100 GbE） optical interconnects has been designed and fabricated in Taiwan Semiconductor Manufacture Company （TSMC） 65nm complementary metal-oxide-semiconductor （CMOS） technology. A novel quadrature voltage-controlled-oscillator （QVCO） structure adopts two pairs of transconductance cell and inverters to acquire rail-to-rail output swing. A half-rate bang-bang phase detector adopts four flip-flops array to sample the 25 Gbit/s input data and align the data phase, so the 25 Gbit/s data are retimed and demultiplexed into two paths 12.5 Gbit/s output data. Experimental results show that the recovered clock exhibits a peak-to-peak jitter of 7.39 ps and the recovered data presents a peak-to-peak jitter of 7.56 ps, in response to 231 - 1 pseudorandom bit sequence （PRBS） input. For 1.2 V voltage supply, the CDR circuit consumes 92 mW （excluding output buffers）.

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

A 5-Gb/s 2 ： 1 MUX （multiplexer） with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment （APA）, has been designed and fabricated in SMIC＇s 0.18 μm CMOS technology. The chip area is 670 × 780 μm^2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

A 2.5-Gb/s fully-integrated,low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery （CDR） circuit has been designed and fabricated in SMIC＇s 0.18-μm CMOS technology. The Pottbiicker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.