A DISCRETE TIME TWO-LEVEL MIXED SERVICE PARALLEL POLLING MODEL

We present a discrete time single-server two-level mixed service polling systems with two queue types, one center queue and N normal queues. Two-level means the center queue will be successive served after each normal queue. In the first level, server visits between the center queue and the normal queue. In the second level, normal queues are polled by a cyclic order. Mixed service means the service discipline are exhaustive for center queue, and parallel 1-limited for normal queues. We propose an imbedded Markov chain framework to drive the closed-form expressions for the mean cycle time, mean queue length, and mean waiting time. Numerical examples demonstrate that theoretical and simulation results are identical the new system efficiently differentiates priorities.

Design of Traffic Light Based on Field Programmable Gate Array

The use of fixed-time traffic lights for road traffic control has the disadvantage of low traffic efficiency. In order to optimize the vehicle traffic at the intersection, this paper proposes a design scheme of a real-time control system for road intelligent traffic lights based on FPGA. The system adopts the polling control model, the vehicle detector detects the arrival rate of vehicles, and obtains the corresponding traffic light green time length according to the traffic rules and polling model theory. Using Altera’s Cyclone IV series EP4CE15E22C8 chip as the development platform, a specific design plan is given. The circuit mainly includes program-controlled amplifier module, AD acquisition module, cross-correlation calculation module, serial port transmission and Lab-VIEW module. The system can realize the intelligent adjustment of traffic lights. Different vehicle arrival rates are detected at different times, so that the corresponding traffic light configuration time length changes accordingly. This intelligent adjustment controls road traffic and makes the main and branch roads coordinate and cooperate, thereby improving the traffic efficiency of the intersection.

CUDA's Mapped Memory to Support I/O Functions on GPU

The API interfaces provided by CUDA help programmers to get high performance CUDA applications in GPU, but they cannot support most I/O operations in device codes. The characteristics of CUDA＇s mapped memory are used here to create a dynamic polling service model in the host which can satisfy most I/O functions such as read/write file and ＂printf＂. The technique to implement these I/O functions has some influence on the performance of the original applications. These functions quickly respond to the users＇ I/O requirements with the ＂printf＂ performance better than CUDA＇s. An easy and effective real-time method is given for users to debug their programs using the I/O functions. These functions improve productivity of converting legacy C/C＋＋ codes to CUDA and broaden CUDA＇s functions.