Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.

Fabrication of Bottom-Gate and Top-Gate Transparent ZnO Thin Film Transistors

Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.

Influence of High Temperature Treatment on the Performance of Nickel-Induced Laterally Crystallized Thin Film Transistors

Well known for their good performance,thin film transistors (TFTs) with active layers which were nickel induced laterally crystallized,are fabricated by conventional process of dual gate CMOS.The influence of pre high temperature treatment of device fabrication on the performance of TFTs is also investigated.The experiment shows that the high temperature treatment affects the performance of the devices strongly.The best performance is obtained by adopting pre treatment of 1000℃.The mobility of 314cm 2/(V·s) is obtained at NMOS TFTs with pre treatment of 1000℃,which is 10% and 22% higher than that treated at 1100℃ and without pre high temperature treatment,respectively.A maximum on/off current ratio of 3×10 8 is also obtained at 1000℃.Further investigation of uniformity verifies that the result is reliable.

Effects of active layer thickness on performance and stability of dual-active-layer amorphous InGaZnO thin-film transistors

Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.

High-photosensitivity polymer thin-film transistors based on poly(3-hexylthiophene)

Polymer thin-film transistors （PTFTs） based on poly（3-hexylthiophene） are fabricated by the spin-coating process, and their photo-sensing characteristics are investigated under steady-state visible-light illumination. The photosensitivity of the device is strongly modulated by gate voltage under various illuminations. When the device is in the subthreshold operating mode, a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10^3 at an illumination intensity of 1200 lx, and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx. However, when the device is in the on-state operating mode, the photosensitivity is very low： only 1.88 at an illumination intensity of 1200 lx for a gate voltage of -20 V and a drain voltage of -20 V. The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light. The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.

Simulation of grain boundary effect on characteristics of ZnO thin film transistor by considering the location and orientation of grain boundary

The grain boundaries （GBs） have a strong effect on the electric properties of ZnO thin film transistors （TFTs）. A novel grain boundary model was developed to analyse the effect. The model was characterized with different angles between the orientation of the grain boundary and the channel direction. The potential barriers formed by the grain boundaries increase with the increase of the grain boundary angle, so the degradation of the transistor characteristics increases. When a grain boundary is close to the drain edge, the potential barrier height reduces, so the electric properties were improved.

Self-assembled monolayers enhance the performance of oxide thin-film transistors

Thin-film transistors(TFTs)based on oxide semiconductors have gained a lot of attention in applications such as displays and sensors particularly in recent years due to the advantages of oxide semiconductors like high mobility,good uniformity over large area and low deposition temperature[1−4].However,the defects/traps at dielectric/channel interface and top surface of oxide TFTs might dramatically degrade device performance including current on/off ratio,mobility and most importantly stability[5,6],making it quite urgent to systematically make effective interface engineering to improve TFT performance.

Preparation and operation characteristics of organic semiconductor transistor using thin film Al gate and copper phthalocyanine

The organic static induction transistors (OSITs) are fabricated by the method of evaporating and plating in a vacuum with copper phthalocyanine (CuPc) dye, and has a five layered structure of Au/CuPc/Al/CuPc/Au. The experiment reveals that OSITs have obtained a low driving voltage, high current density and high switch speed such as I_ DS = 1.2×10 -6 A/mm2, and the degree of 1 000 Hz. The OSITs have excellent operation characteristics of typical static induction transistors.

Carrier Transport Across Grain Boundaries in Polycrystalline Silicon Thin Film Transistors

We established a model for investigating polycrystalline silicon（poly-Si） thin film transistors（TFTs）.The effect of grain boundaries（GBs） on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region,and the dominant transport mechanism of carrier across grain boundaries was subsequently determined.It is shown that the thermionic emission（TE） is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary.To a poly-Si TFT model with a 1 nm-width grain boundary,in the linear region,thermionic emission is similar to that of tunneling（TU）,however,with increasing grain boundary width and number,tunneling becomes dominant.

High-Performance Photo-Modulated Thin-Film Transistor Based on Quantum dots/Reduced Graphene Oxide Fragment-Decorated ZnO Nanowires

In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of Cd Se quantum dots and reduced graphene oxide(RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 AW^(-1) and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.

Effects of annealing process on characteristics of fully transparent zinc tin oxide thin-film transistor

Annealing effect on the performance of fully transparent thin-film transistor （TTFT）, in which zinc tin oxide （ZnSnO） is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/（V.s） and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

The instability of p-channel low-temperature polycrystalline silicon thin film transistors(poly-Si TFTs)is investigated under negative gate bias stress(NBS)in this work.Firstly,a series of negative bias stress experiments is performed,the significant degradation behaviors in current-voltage characteristics are observed.As the stress voltage decreases from-25 V to-37 V,the threshold voltage and the sub-threshold swing each show a continuous shift,which is induced by gate oxide trapped charges or interface state.Furthermore,low frequency noise(LFN)values in poly-Si TFTs are measured before and after negative bias stress.The flat-band voltage spectral density is extracted,and the trap concentration located near the Si/SiO2 interface is also calculated.Finally,the degradation mechanism is discussed based on the current-voltage and LFN results in poly-Si TFTs under NBS,finding out that Si-OH bonds may be broken and form Si*and negative charge OH-under negative bias stress,which is demonstrated by the proposed negative charge generation model.

Properties of C_(60) thin film transistor based on polystyrene

This paper reports that the n-type organic thin-fihn transistors have been fabricated by using C60 as the active layer and polystyrene as the dielectric. The properties of insulator and the growth characteristic of C60 film were carefully investigated. By choosing different source/drain electrodes, a device with good performance can be obtained. The highest electron field effect mobility about 1.15 cm2/（V. s） could reach when Barium was introduced as electrodes. Moreover, the C60 transistor shows a negligible ＇hysteresis effect＇ contributed to the hydroxyl-free of insulator. The result suggests that polymer dielectrics are promising in applications among n-type organic transistors.

Numerical study on the dependence of ZnO thin-film transistor characteristics on grain boundary position

The dependence of transistor characteristics on grain boundary （GB） position in short-channel ZnO thin film transistors （TFTs） has been investigated using two-dimensional numerical simulations. To simulate the device accurately, both tail states and deep-level states are taken into consideration. It is shown that both the transfer and output characteristics of ZnO TFTs change dramatically with varying GB position, which is different from polycrystalline Si （poly-Si） TFTs. By analysing the mechanism of the carrier transportation in the device, it is revealed that the dependence is derived from the degrees of carrier concentration descent and mobility variation with CB position.

Modeling of polycrystalline ZnO thin-film transistors with a consideration of the deep and tail states

We report a model of the carrier transport and the subgap density of states in a polycrystalline ZnO film for simulating a polycrystalline ZnO thin film transistor. This simple model considering the deep and the band tail states reproduces well the characteristics of polycrystalline ZnO thin film transistors. Furthermore, using the developed model, we study the effects of defect parameters on the electrical performances of the polycrystalline ZnO thin film transistors.

Degradation of current–voltage and low frequency noise characteristics under negative bias illumination stress in InZnO thin film transistors

The instabilities of indium–zinc oxide thin film transistors under bias and/or illumination stress are studied in this paper. Firstly, illumination experiments are performed, which indicates the variations of current–voltage characteristics and electrical parameters（such as threshold voltage and sub-threshold swing） are dominated by the stress-induced ionized oxygen vacancies and acceptor-like states. The dependence of degradation on light wavelength is also investigated. More negative shift of threshold voltage and greater sub-threshold swing are observed with the decrease of light wavelength.Subsequently, a negative bias illumination stress experiment is carried out. The degradation of the device is aggravated due to the decrease of recombination effects between ionized oxygen vacancies and free carriers. Moreover, the contributions of ionized oxygen vacancies and acceptor-like states are separated by using the mid-gap method. In addition, ionized oxygen vacancies are partially recombined at room temperature and fully recombined at high temperature. Finally, low-frequency noise is measured before and after negative bias illumination stress. Experimental results show few variations of the oxide trapped charges are generated during stress, which is consistent with the proposed mechanism.

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium-gallium-zinc oxide thin film transistor, which adopts an elevated-metal metal-oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction. The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the back-channel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device （L=2 μm）. It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.