Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

实际应用条件下Power MOSFET开关特性研究(上)

针对实际应用中Power MOSFET开关工作状况与现有文献的描述有很大不同,使用不当易造成器件的损坏和设备的崩溃这一现象,在应用条件下对Power MOSFET开关特性进行了研究,深入分析了Power MOSFET的开关过程,提出了关于开关过程四阶段的新观点,并采用对开关过程的等效输入电容进行分段线性化的新方法对不同阶段的开关参数进行了计算,搭建了开关特性实验电路,实验结果表明,提出的Power MOSFET开关过程四阶段的新观点是正确的,等效输入电容分段线性化的新方法是合理的。

实际应用条件下Power MOSFET开关特性研究(下)

从功率MOSFET内部结构和极间电容的电压依赖关系出发,对功率MOSFET的开关现象及其原因进行了较深入分析。从实际应用的角度,对功率MOSFET开关过程的功率损耗和所需驱动功率进行了研究,提出了有关参数的计算方法,并对多种因素对开关特性的影响效果进行了实验研究,所得出的结论对于功率MOSFET的正确运用和设计合理的MOSFET驱动电路具有指导意义。

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investigated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching frequency of SiC power MOSFETs.

不同型号的星用Power MOSFET的辐射响应特性

利用60Co源对将应用于空间系统的两种Power MOSFET进行了不同总剂量辐照实验,并从微观氧化物陷阱电荷和界面态的辐射感生角度,对比分析了不同型号Power MOSFET器件在60Coγ射线辐射下的总剂量效应以及辐照后100℃下退火特性,并侧重分析了总剂量实验中阈值电压和击穿电压的变化关系。为此类器件在航天系统中的应用提供了辐照数据基础和依据。

应用于空间系统的Power MOSFET辐射响应特性

为给金属氧化物半导体场效应功率管(PowerMOSFET)在航天系统中的应用提供辐照数据基础和依据。用60Co源对将应用于空间系统的两种PowerMOSFET进行了不同总剂量的辐照实验。从微观氧化物陷阱电荷和界面态的辐射感生角度,分析了PowerMOSFET器件在60Coγ射线辐射下的总剂量和剂量率效应以及辐照后70℃退火特性。试验表明与N沟道PowerMOSFET相比,P沟道PowerMOSFET可能更适合空间应用。

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

功率变换器中Power MOSFET功率损耗的数学分析及计算

为改善中、低压电力电子设备中开关器件的性能,给出了一种功率变换器的Power MOS-FET开关电路模型。其Power MOSFET的功率损耗主要由导通损耗和开关损耗构成,由此推导了功率变换器主电路中Power MOSFET的损耗计算公式,并根据实验波形的计算,得到Power MOS-FET的功率损耗。得到的计算结果表明:当开关频率较大时,开关损耗是Power MOSFET功率损耗的主要部分。

高压大功率SiC MOSFETs短路保护方法

碳化硅(SiC)MOSFETs短路承受能力弱,研究其短路保护方法成为保障电力电子设备安全运行的重要课题。现有方法大多围绕低压小功率SiC MOSFETs,然而随着电压和功率等级的提升,器件特性有所差异,直接套用以往设计难以实现高压大功率SiC MOSFETs的快速、可靠保护。该文首先详细研究了几种常用短路检测方法;其次基于高压大功率SiC MOSFETs器件特性,深入对比分析了不同短路检测方法的适用性,提出一种阻容式漏源极电压检测和栅极电荷检测相结合的短路保护方法;最后搭建了实验平台验证所提方法的可行性。结果表明,提出的方法在硬开关短路故障(hard switching fault,HSF)下,保护响应时间缩短了1.4μs,短路能量降低了62.5%;且能可靠识别负载短路故障(fault under load,FUL)。

空间辐射环境下SiC功率MOSFET栅氧长期可靠性研究

利用等效1 MeV中子和γ射线对1200 V SiC功率MOSFET进行辐射,研究了电离损伤和位移损伤对器件的影响,并分析了辐射后器件栅氧长期可靠性。结果表明:中子辐射后器件导通电阻发生明显退化,与辐射引入近界面缺陷降低载流子寿命和载流子迁移率有关。时间依赖的介质击穿(TDDB)结果表明,栅泄漏电流呈现先增加后降低趋势,与空穴捕获和电子捕获效应有关。中子辐射后栅漏电演化形式未改变,但氧化层击穿时间增加,这是中子辐射缺陷增加了Fowler-Nordheim(FN)隧穿势垒的缘故。总剂量辐射在器件氧化层内引入陷阱电荷,使得器件阈值电压负向漂移。随后的TDDB测试表明,与中子辐射一致,总剂量辐射未改变栅漏电演化形式,但氧化层击穿时间提前。这是总剂量辐射在氧化层内引入额外空穴陷阱和中性电子陷阱的缘故。

功率MOSFET抗单粒子加固技术研究

针对功率MOSFET的单粒子效应(SEE)开展了工艺加固技术研究,在单粒子烧毁(SEB)加固方面采用优化的体区掺杂工艺,有效降低了寄生双极晶体管(BJT)增益,抑制了单粒子辐照下的电流正反馈机制。在单粒子栅穿(SEGR)加固方面,通过形成缓变掺杂的外延缓冲层来降低纵向电场梯度,减弱了非平衡载流子在栅敏感区的累积,并开发了台阶栅介质结构提升栅敏感区的临界场强。实验结果表明,经过加固的功率MOSFET在满额漏源工作电压和15 V栅源负偏电压的偏置条件下,单粒子烧毁和栅穿LET值大于75 MeV·cm^(2)/mg。在相同辐照条件下,加固器件的栅源负偏电压达到15~17 V,较加固前的7~10 V有显著提升。

高速SiC-MOSFET叠层封装结构设计及性能评估

作为脉冲系统的核心部件,开关承担着脉冲成形、功率调制等重要作用,开关通断速度往往决定脉冲上升时间,高速开关是纳秒短脉冲形成的关键。提出一种高速SiC-MOSFET叠层封装结构,整体布局无引线、无外接,具有极低寄生电感。开展了电磁场仿真研究,揭示了脉冲形成过程中封装多介质界面电磁场分布规律,明确了封装结构电磁薄弱环节,为进一步绝缘优化提供指导。搭建双脉冲测试平台,对研制的SiC-MOSFET叠层封装开关与同芯片商用TO-263-7封装开关的动态性能进行测试。结果表明,大电流工况下,所提封装电流开通速度提升48%,关断速度提升50%,开通损耗降低54.6%,关断损耗降低62.8%,实验结果验证了所提叠层封装结构对开关动态性能的改善。

Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation. The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range （-55 to 150 ℃）. An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism. The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature. The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.

SEGR-and SEB-hardened structure with DSPSOI in power MOSFETs

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture （SEGR） and single event burnout （SEB）, which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOS- FETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator （DSPSOI） layers. Results show that the safety operation area （SOA） of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV-cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

A novel silicon-on-insulator（SOI） MOSFET with a variable low-k dielectric trench（LDT MOSFET） is proposed and its performance and characteristics are investigated.The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region.At OFF state,the low-k dielectric trench（LDT） can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time,the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally,ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics,such as low gateto -drain charge density（〈 0.6 nC/mm^2） and a robust safe operating area（0-84 V）.

Charge deposition model for investigating SE-microdose effect in trench power MOSFETs

It was demonstrated that heavy ions can induce large current-voltage （I-V） characteristics shift in commercial trench power MOSFETs, named single event microdose effect （SE-microdose effect）. A model is pre- sented to describe this effect. This model calculates the charge deposition by a single heavy ion hitting oxide and the subsequent charge transport under an electric field. Holes deposited at the SiO2/Si interface by a Xe ion are calculated by using this model. The calculated results were then used in Sentaurus TCAD software to simulate a trench power MOSFET＇s I-V curve shift after a Xe ion has hit it. The simulation results are consistent with the related experiment＇s data. In the end, several factors which affect the SE-microdose effect in trench power MOSFETs are investigated by using this model.

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout（SEB） hardened planar power MOSFET with partially widened trench sources by three-dimensional（3 D） numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region（P-well region below the N＋ source）. The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer（LET）,which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to0.7 p C/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor （MOSFET） drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.

The investigation of the zero temperature coefficient point of power MOSFET

The paper investigates the zero temperature coefficient（ZTC） point of power MOSFET,based on the output characteristic of power MOSFET,the temperature coefficient of threshold voltage and the carrier mobility.It is found that the gate voltage has a big effect on the ZTC point.The result indicates that there are three types of temperature coefficient under different gate voltage.When the gate voltage is near the threshold voltage,both the linear region and saturation region shows a large positive temperature coefficient.With the increase of gate voltage,the temperature coefficient of the linear region changes from positive to negative,when the saturation region still remains positive,giving rise to the ZTC point.When the gate voltage is high enough,the negative temperature coefficient is present on both the linear and saturation region,resulting in no ZTC point.According to the experimental result,the change of ZTC point as a function of temperature is larger when the gate voltage is higher.The carrier mobility is also discussed,displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.