A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM ...A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm^2.展开更多
We experimentally demonstrate a small-size and high-speed silicon optical switch based on the free carrier plasma dispersion in silicon. Using an embedded racetrack resonator with a quality factor of 7400, the optical...We experimentally demonstrate a small-size and high-speed silicon optical switch based on the free carrier plasma dispersion in silicon. Using an embedded racetrack resonator with a quality factor of 7400, the optical switch shows an extinction ratio exceeding 13 dB with a footprint of only 2.2 × 10-3 mm^2. Moreover, a novel pre-emphasis technique is introduced to improve the optical response performance and the rise and the fall times are reduced down to 0.24 ns and 0.42 ns respectively, which are 25% and 44% lower than those without the pre-emphasis.展开更多
This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A...This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.展开更多
This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes...This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.展开更多
This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and con...This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010403)the National Natural Science Foundation of China(No.60801045)
文摘A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode（VM） and current mode（CM） output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm^2.
基金Project supported by the National Natural Science Foundation of China(Grant No.60877036)the National Basic Research Program of China(Grant No.2006CB302803)+1 种基金the State Key Laboratory of Advanced Optical Communication Systems and Networks,China(Grant No.2008SH02)the Knowledge Innovation Program of Institute of Semiconductors,Chinese Academy of Sciences(Grant No.ISCAS2008T10)
文摘We experimentally demonstrate a small-size and high-speed silicon optical switch based on the free carrier plasma dispersion in silicon. Using an embedded racetrack resonator with a quality factor of 7400, the optical switch shows an extinction ratio exceeding 13 dB with a footprint of only 2.2 × 10-3 mm^2. Moreover, a novel pre-emphasis technique is introduced to improve the optical response performance and the rise and the fall times are reduced down to 0.24 ns and 0.42 ns respectively, which are 25% and 44% lower than those without the pre-emphasis.
基金supported by the National Natural Science Foundation of China under Grant No. 61006027the New Century Excellent Talents Program under Grant No. NCET-10-0297
文摘This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.
基金Project supported by the National Natural Science Foundation of China(No.60676016)
文摘This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC＇s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm^2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.
文摘This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.
