Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enabl...Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closedform expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.展开更多
Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges.Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis lo...Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges.Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis loops with erroneous rem-nant polarization(P_(r))and coercive field(E_(c)).In this study,positive-up-negative-down(PUND)measurement under a wide fre-quency range was performed on a 10-nm thick Hf_(0.5)Zr_(0.5)O_(2) ferroelectric film.Detailed analysis on the leakage current and RC delay was conducted as the polarization switching occurs in the FE capacitor.After considering the time lag caused by RC delay,reasonable calibration of current response over the voltage pulse stimulus was employed in the integral of polarization current over time.In such a method,rational P-V loops measured at high frequencies(>1 MHz)was successfully achieved.This work provides a comprehensive understanding on the effect of parasitic factors on the polarization switching behavior of FE films.展开更多
By utilizing the first order behavior of the device,an equation for the frequency of operation of the submicron CMOS ring oscillator is presented.A 5-stage ring oscillator is utilized as the initial design,with differ...By utilizing the first order behavior of the device,an equation for the frequency of operation of the submicron CMOS ring oscillator is presented.A 5-stage ring oscillator is utilized as the initial design,with different Beta ratios,for the computation of the operating frequency.Later on,the circuit simulation is performed from 5-stage till 23-stage,with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively.It is noted that the output frequency is inversely proportional to the square of the device length,and when the value of Beta ratio is used as 2.3,a difference of 3.64%is observed on an average,in between the computed and the simulated values of frequency.As an outcome,the derived equation can be utilized,with the inclusion of an empirical constant in general,for arriving at the ring oscillator circuit’s output frequency.展开更多
文摘Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closedform expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.
基金supported by the Ministry of Science and Technology(MOST)of China under Grant 2016YFA0203800in part by the National Natural Science Foundation of China under Grants 61834009,62025406,92064003,61821091the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant XDB44010300。
文摘Ferroelectric hysteresis loop measurement under high driving frequency generally faces great challenges.Parasitic factors in testing circuits such as leakage current and RC delay could result in abnormal hysteresis loops with erroneous rem-nant polarization(P_(r))and coercive field(E_(c)).In this study,positive-up-negative-down(PUND)measurement under a wide fre-quency range was performed on a 10-nm thick Hf_(0.5)Zr_(0.5)O_(2) ferroelectric film.Detailed analysis on the leakage current and RC delay was conducted as the polarization switching occurs in the FE capacitor.After considering the time lag caused by RC delay,reasonable calibration of current response over the voltage pulse stimulus was employed in the integral of polarization current over time.In such a method,rational P-V loops measured at high frequencies(>1 MHz)was successfully achieved.This work provides a comprehensive understanding on the effect of parasitic factors on the polarization switching behavior of FE films.
文摘By utilizing the first order behavior of the device,an equation for the frequency of operation of the submicron CMOS ring oscillator is presented.A 5-stage ring oscillator is utilized as the initial design,with different Beta ratios,for the computation of the operating frequency.Later on,the circuit simulation is performed from 5-stage till 23-stage,with the range of oscillating frequency being 3.0817 and 0.6705 GHz respectively.It is noted that the output frequency is inversely proportional to the square of the device length,and when the value of Beta ratio is used as 2.3,a difference of 3.64%is observed on an average,in between the computed and the simulated values of frequency.As an outcome,the derived equation can be utilized,with the inclusion of an empirical constant in general,for arriving at the ring oscillator circuit’s output frequency.
