提出了一种射频接收机中自动增益控制(Automatic Gain Control,AGC)电路的建模方法和设计方法。该建模方法对射频接收机中自动增益控制电路进行了建模分析和理论推导,得到3 种常见电路拓扑的时间常数公式。通过电子设计软件对该模型进...提出了一种射频接收机中自动增益控制(Automatic Gain Control,AGC)电路的建模方法和设计方法。该建模方法对射频接收机中自动增益控制电路进行了建模分析和理论推导,得到3 种常见电路拓扑的时间常数公式。通过电子设计软件对该模型进行仿真验证,得到的时域分析结果与模型计算相吻合。对采用模型参数的接收机电路进行了制作和测试,与模型计算和仿真结果匹配良好。该方法解决了射频接收机中自动增益控制电路不同时间常数的设计难题,对精细自动增益控制电路设计提供理论指导。展开更多
在大动态范围的复杂通信系统中,自动增益控制系统的性能起着至关重要的作用。针对传统自动增益控制系统的动态范围较小及收敛速度较慢的问题,提出了一种大动态范围数字AGC快速控制算法。该算法采用射频峰值检测以及大信号指示的方式实...在大动态范围的复杂通信系统中,自动增益控制系统的性能起着至关重要的作用。针对传统自动增益控制系统的动态范围较小及收敛速度较慢的问题,提出了一种大动态范围数字AGC快速控制算法。该算法采用射频峰值检测以及大信号指示的方式实现对射频功率的快速检测;采用平均功率的方式对中频信号功率进行滑动平均,准确获取中频信号的平均功率;结合中频和射频增益控制策略,对接收信道的增益进行分配以及快速控制,使得射频信号经过射频单元后始终位于模数转换器(Analog to Digital Converter,ADC)的动态范围内,从而实现射频信号的稳定接收。仿真结果表明,相较于传统算法,所提算法的收敛时间由毫秒级提高到了微秒级,动态范围大幅提升。展开更多
A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz...A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.展开更多
文摘提出了一种射频接收机中自动增益控制(Automatic Gain Control,AGC)电路的建模方法和设计方法。该建模方法对射频接收机中自动增益控制电路进行了建模分析和理论推导,得到3 种常见电路拓扑的时间常数公式。通过电子设计软件对该模型进行仿真验证,得到的时域分析结果与模型计算相吻合。对采用模型参数的接收机电路进行了制作和测试,与模型计算和仿真结果匹配良好。该方法解决了射频接收机中自动增益控制电路不同时间常数的设计难题,对精细自动增益控制电路设计提供理论指导。
文摘在大动态范围的复杂通信系统中,自动增益控制系统的性能起着至关重要的作用。针对传统自动增益控制系统的动态范围较小及收敛速度较慢的问题,提出了一种大动态范围数字AGC快速控制算法。该算法采用射频峰值检测以及大信号指示的方式实现对射频功率的快速检测;采用平均功率的方式对中频信号功率进行滑动平均,准确获取中频信号的平均功率;结合中频和射频增益控制策略,对接收信道的增益进行分配以及快速控制,使得射频信号经过射频单元后始终位于模数转换器(Analog to Digital Converter,ADC)的动态范围内,从而实现射频信号的稳定接收。仿真结果表明,相较于传统算法,所提算法的收敛时间由毫秒级提高到了微秒级,动态范围大幅提升。
基金Project supported by the Science and Technology Innovation Project for the Postgraduates of National University of Defense Technology
文摘A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.
