A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2...A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900 MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The normal mode receiver in the presence of -3 dBm self-jammer achieves -75 dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25 dBm OP1 dB output power for CW. The fully-integrated fractional-N fre-quency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8 GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106 dBc/Hz@200 kHz and -131 dBc/Hz@1 MHz offset from center frequency and the integrated RMS jitter from 10 kHz to 10 MHz is less than 1.6 pS. The chip dissipates 330 mA from 3.3 V power supply when transmitting 22.4 dBm CW signal and the PAE of linear PA is up to 26%. The chip die area is 16.8 mm2.展开更多
随着射频识别(Radio Frequency Identification,RFID)技术的发展,人们对其应用的要求越来越高,在阅读器部署方面的研究也逐渐深入。为了解决规定区域内RFID阅读器位置规划问题,在划定的区域内,以标签覆盖率、阅读器间的碰撞干扰、负载...随着射频识别(Radio Frequency Identification,RFID)技术的发展,人们对其应用的要求越来越高,在阅读器部署方面的研究也逐渐深入。为了解决规定区域内RFID阅读器位置规划问题,在划定的区域内,以标签覆盖率、阅读器间的碰撞干扰、负载均衡为目标来建立数学优化模型,在白鲸算法的基础上提出了一种改进型白鲸算法。首先,针对标准白鲸算法存在易陷入局部最优、丢失次优解的缺陷,提出了一种更新精英群体机制;其次,为了增强算法的探索能力,加入了反向学习策略;最后,运用该算法来解决RFID网络规划问题。通过在一定环境中放置不同数量集群和随机分布的标签,将改进型白鲸算法与粒子群算法、灰狼算法和标准白鲸算法进行对比。仿真结果表明,在相同环境下,改进型白鲸算法的性能相比粒子群算法平均提高了21.1%,比灰狼算法提高了28.5%,比白鲸算法提高了3.3%,说明该算法相比其他3种算法在搜索精度上具有更好的性能,并通过阅读器优化部署测试,验证了该应用的有效性和可行性。展开更多
RFID(Radio Frequency Identification,射频识别)通过自动识别帮助机器或计算机识别对象,记录元数据或通过无线电波控制单个目标等。当RFID阅读器与Internet终端相连接时,阅读器可以根据需要全局、自动、实时地识别,跟踪和监视带有标签...RFID(Radio Frequency Identification,射频识别)通过自动识别帮助机器或计算机识别对象,记录元数据或通过无线电波控制单个目标等。当RFID阅读器与Internet终端相连接时,阅读器可以根据需要全局、自动、实时地识别,跟踪和监视带有标签的对象。研究从基于FPGA(Field Programmable Gate Array,现场可编程逻辑门阵列)的RFID阅读器三个方面入手进行阐述:整体、硬件部分和软件部分。首先论述阅读器的整体构成、天线以及数字基带结构,然后从硬件部分和软件部分细致地对阅读器进行剖析阐述,最后进行了仿真模拟。展开更多
无线射频识别技术(Radio Frequency Identification,RFID)具有无需直接接触即可读取数据的特性,已广泛应用于自动识别和数据捕获系统,特别是地铁票卡系统中。通过使用RFID技术,地铁票卡读写器系统不仅能提高票卡处理速度,还能增强数据...无线射频识别技术(Radio Frequency Identification,RFID)具有无需直接接触即可读取数据的特性,已广泛应用于自动识别和数据捕获系统,特别是地铁票卡系统中。通过使用RFID技术,地铁票卡读写器系统不仅能提高票卡处理速度,还能增强数据的安全性和处理能力。本文深入探讨了基于RFID技术的地铁票卡读写器系统的设计与优化,包括系统需求分析、数据处理、读写识别技术的优化以及整体系统功能的实现,并通过系列系统测试验证了所提出优化措施的有效性。展开更多
To implement a fully-integrated on-chip CMOS power amplifier(PA) for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as...To implement a fully-integrated on-chip CMOS power amplifier(PA) for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency(PAE) is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.展开更多
A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and ...A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.展开更多
A low cost fully integrated single-chip UHF radio frequency identification(RFID) reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a...A low cost fully integrated single-chip UHF radio frequency identification(RFID) reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is-60 dBm.The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW.The chip has a die area of 5.1×3.8 mm^2 including pads.展开更多
A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an ...A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.展开更多
文摘A single-chip UHF RFID reader transceiver IC has been implemented in 0.18 μm SiGe BiCMOS technology. The chip includes all transceiver blocks as RX/TX RF front-end, RX/TX analog baseband, frequency synthesizer and I2C with fully-compliant China 800/900 MHz RFID draft, ISO/IEC 18000-6C protocol and ETSI 302 208-1 local regulation. The normal mode receiver in the presence of -3 dBm self-jammer achieves -75 dBm 1% PER sensitivity. The linear class-A PA integrated in transmitter has 25 dBm OP1 dB output power for CW. The fully-integrated fractional-N fre-quency synthesizer is designed based on MASH 1-1-1 sigma-delta modulator and 1.8 GHz fundamental frequency LC-VCO for lower in-band and out-of-band phase noise. The measured phase noise is up to -106 dBc/Hz@200 kHz and -131 dBc/Hz@1 MHz offset from center frequency and the integrated RMS jitter from 10 kHz to 10 MHz is less than 1.6 pS. The chip dissipates 330 mA from 3.3 V power supply when transmitting 22.4 dBm CW signal and the PAE of linear PA is up to 26%. The chip die area is 16.8 mm2.
文摘随着射频识别(Radio Frequency Identification,RFID)技术的发展,人们对其应用的要求越来越高,在阅读器部署方面的研究也逐渐深入。为了解决规定区域内RFID阅读器位置规划问题,在划定的区域内,以标签覆盖率、阅读器间的碰撞干扰、负载均衡为目标来建立数学优化模型,在白鲸算法的基础上提出了一种改进型白鲸算法。首先,针对标准白鲸算法存在易陷入局部最优、丢失次优解的缺陷,提出了一种更新精英群体机制;其次,为了增强算法的探索能力,加入了反向学习策略;最后,运用该算法来解决RFID网络规划问题。通过在一定环境中放置不同数量集群和随机分布的标签,将改进型白鲸算法与粒子群算法、灰狼算法和标准白鲸算法进行对比。仿真结果表明,在相同环境下,改进型白鲸算法的性能相比粒子群算法平均提高了21.1%,比灰狼算法提高了28.5%,比白鲸算法提高了3.3%,说明该算法相比其他3种算法在搜索精度上具有更好的性能,并通过阅读器优化部署测试,验证了该应用的有效性和可行性。
文摘无线射频识别技术(Radio Frequency Identification,RFID)具有无需直接接触即可读取数据的特性,已广泛应用于自动识别和数据捕获系统,特别是地铁票卡系统中。通过使用RFID技术,地铁票卡读写器系统不仅能提高票卡处理速度,还能增强数据的安全性和处理能力。本文深入探讨了基于RFID技术的地铁票卡读写器系统的设计与优化,包括系统需求分析、数据处理、读写识别技术的优化以及整体系统功能的实现,并通过系列系统测试验证了所提出优化措施的有效性。
文摘To implement a fully-integrated on-chip CMOS power amplifier(PA) for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency(PAE) is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.
基金Project supported by the Ministry of Science & Technology of China(No.2008BAI55B07)
文摘A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA04A102).
文摘A low cost fully integrated single-chip UHF radio frequency identification(RFID) reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is-60 dBm.The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW.The chip has a die area of 5.1×3.8 mm^2 including pads.
基金Project supported by the National High Technology Research and Development Program of China (Nos.2006AA04A109,2008AA010708)
文摘A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.