This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share ...This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.展开更多
Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
文摘This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
