WinoNet:Reconfigurable look-up table-based Winograd accelerator for arbitrary precision convolutional neural network inference

To solve the hardware deployment problem caused by the vast demanding computational complexity of convolutional layers and limited hardware resources for the hardware network inference,a look-up table(LUT)-based convolution architecture built on a field-programmable gate array using integer multipliers and addition trees is used.With the help of the Winograd algorithm,the optimization of convolution and multiplication is realized to reduce the computational complexity.The LUT-based operator is further optimized to construct a processing unit(PE).Simultaneously optimized storage streams improve memory access efficiency and solve bandwidth constraints.The data toggle rate is reduced to optimize power consumption.The experimental results show that the use of the Winograd algorithm to build basic processing units can significantly reduce the number of multipliers and achieve hardware deployment acceleration,while the time-division multiplexing of processing units improves resource utilization.Under this experimental condition,compared with the traditional convolution method,the architecture optimizes computing resources by 2.25 times and improves the peak throughput by 19.3 times.The LUT-based Winograd accelerator can effectively solve the deployment problem caused by limited hardware resources.

可用于HDTV解码器的基于ROM查找表的IDCT电路大规模集成电路实现

介绍了采用基于ROM查找表的全数字反离散余弦变换(IDCT)电路的算法原理及其并行架构的大规模集成电路实现.首先将二维IDCT转换为两个一维IDCT变换,根据蝶形算法进一步转换为矩阵的乘加运算.通过将连续输入的一个块的奇列或偶列的4个数据进行数据位重排,即将4个数据中相同的位组合在一起,则可用一个ROM查找表实现不同位的乘加运算.避免了硬件上的乘法器开销,具有很高的实现效率并节省硬件资源面积,因此可用于HDTV的实时解码器中,有助于降低电路的功耗.该电路已用于已开发的MPEG-2 MP@HL高清解码芯片,采用0.18μmCMOS工艺成功进行了流片.

Area and Speed Efficient Implementation of Symmetric FIR Digital Filter through Reduced Parallel LUT Decomposed DA Approach

This brief proposes an area and speed efficient implementation of symmetric finite impulse response (FIR) digital filter using reduced parallel look-up table (LUT) distributed arithmetic (DA) based approach. The complexity lying in the realization of FIR filter is dominated by the multiplier structure. This complexity grows further with filter order, which results in increased area, power, and reduced speed of operation. The speed of operation is improved over multiply-accumulate approach using multiplier less conventional DA based design and decomposed DA based design. Both the structure requires B clock cycles to get the filter output for the input width of B, which limits the speed of DA structure. This limitation is addressed using parallel LUTs, called high speed DA FIR, at the expense of additional hardware cost. With large number of taps, the number of LUTs and its size also becomes large. In the proposed method, by exploiting coefficient symmetry property, the number of LUTs in the decomposed DA form is reduced by a factor of about 2. This proposed approach is applied in high speed DA based FIR design, to obtain area and speed efficient structure. The proposed design offers around 40% less area and 53.98% less slice-delay product (SDP) than the high throughput DA based structure when it’s implemented over Xilinx Virtex-5 FPGA device-XC5VSX95T-1FF1136 for 16-tap symmetric FIR filter. The proposed design on the same FPGA device, supports up to 607 MHz input sampling frequency, and offers 60.5% more speed and 67.71% less SDP than the systolic DA based design.

PERFORMANCE IMPROVEMENT FOR A WCDMA RADIO OVER FIBER SYSTEM USING DIGITAL PRE-DISTORTER

In this paper,a Radio Over Fiber (ROF) system with a Digital Pre-Distorter (DPD) for WCDMA signal transmission is investigated.A Look-Up Table (LUT) based DPD and a Memory Polynomial (MP) DPD are applied in the ROF link so as to suppress the out-of-band spurious spectrum and improve the transmission performance.The experimental results show that the out-of-band emission due to existence of the third-order Inter-Modulation Distortion (IMD3) is obviously sup-pressed by these two DPD.An Adjacent Channel Power Ratio (ACPR) improvement of 8 dB is ob-tained for a single-carrier WCDMA signal transmission.These two DPD have equal ability in lin-earization of the ROF system for a three-carrier WCDMA signal transmission.There is no apparent memory effects exist in the ROF link.

The Real Time Mixing Module Design for HDTV Data of SMPTE 274M and PC Video Data

A real time mixing module for high definition television (HDTV) data of SMPTE 274M and PC video data is designed. The hardware implementation, algorithm and simulation of the mixing module are given. In order to improve the capability of data processing, an anti-fuse FPGA chip and a mechanism of pipelining and modularization are adopted. With 6 parallel LUTs and a fast algorithm, it can mix 4∶2∶2 component signals in luminance and chrominance space respectively in real time. According to the simulation, the module has the ability to mix the uncompressed HDTV data with PC video data in real time, which can not be fulfilled by current ASIC chips. Furthermore, it can be extended to multi-stage mixing with the thoughts implied by the design. The mixing module can be widely used in HDTV production systems.