Based on the Berlekamp-Massy （BM） algorithm for Reed-Solomon（RS） decoding, an improved version is proposed, which focuses on how to find the error locator polynomial using least iterative operations. The condition...Based on the Berlekamp-Massy （BM） algorithm for Reed-Solomon（RS） decoding, an improved version is proposed, which focuses on how to find the error locator polynomial using least iterative operations. The conditions to end the iterative operations is derived. As a special case, criterion of only one error symbol in one received codeword is derived as well. Steps are listed concerning the implementation of the improved iterative decoding algorithm, which is carried out as software on the platform of TI＇s C6416 DSP. Decoding performance and decoding-delay of both improved and original algorithms under different （n,k） conditions are simulated. The results of simulations demonstrate that the improved algorithm has less computational complexity when the number of errors in a received codeword is relatively small. Therefore, in channels with low noise power spectrum density, the improved algorithm results in less decoding-delay than BM algorithm.展开更多
This paper focuses on the forward error correction(FEC),the basic parameters determination of the RS convolution code,Turbo code and the LDPC code,and the corresponding encoding and decoding algorithm in power line co...This paper focuses on the forward error correction(FEC),the basic parameters determination of the RS convolution code,Turbo code and the LDPC code,and the corresponding encoding and decoding algorithm in power line communication(PLC)standard.Simulation experiment which is designed for narrow-band power line communication system based on OFDM is done.The coding using RS convolution code,Turbo code and LDPC code are compared,and further it is determined that which encoding method is more suitable for power line communication in China.展开更多
An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatur...An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.展开更多
基金Sponsored by the National High Technology Research and Development Program of China ("863"Program) (2007AA01Z293)
文摘Based on the Berlekamp-Massy （BM） algorithm for Reed-Solomon（RS） decoding, an improved version is proposed, which focuses on how to find the error locator polynomial using least iterative operations. The conditions to end the iterative operations is derived. As a special case, criterion of only one error symbol in one received codeword is derived as well. Steps are listed concerning the implementation of the improved iterative decoding algorithm, which is carried out as software on the platform of TI＇s C6416 DSP. Decoding performance and decoding-delay of both improved and original algorithms under different （n,k） conditions are simulated. The results of simulations demonstrate that the improved algorithm has less computational complexity when the number of errors in a received codeword is relatively small. Therefore, in channels with low noise power spectrum density, the improved algorithm results in less decoding-delay than BM algorithm.
基金This work was supported by the State Key Lab of Power System,Tsinghua University,Beijing,China(SKLD11KM05).
文摘This paper focuses on the forward error correction(FEC),the basic parameters determination of the RS convolution code,Turbo code and the LDPC code,and the corresponding encoding and decoding algorithm in power line communication(PLC)standard.Simulation experiment which is designed for narrow-band power line communication system based on OFDM is done.The coding using RS convolution code,Turbo code and LDPC code are compared,and further it is determined that which encoding method is more suitable for power line communication in China.
文摘An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.
