Design and implementation of control system for superconducting RSFQ circuit

The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.

Design of a finite impulse response filter for rapid single-flux-quantum signal processors based on stochastic computing

Rapid‐Single‐Flux‐Quantum(RSFQ)circuit technology is well known for its low power consumption and latency,which enables digital signal processing up to tens of GHz.As a fundamental digital filter,the Finite Impulse Response(FIR)filter has wide applications in communication systems.A design of an FIR filter based on RSFQ circuit technology is proposed.However,the FIR filter consumes large amounts of adders and multipliers.Based on Stochastic Computing(SC)theory with which adder and multiplier are much simpler,the hardware cost of FIR filter is dramatically reduced.A novel stochastic number generator(SNG),a stochastic‐tobinary converter(SBC),and the FIR filter were designed and verified via logic simulation with a target frequency of 10 GHz.The results indicated the FIR filter performs correct operations.The proposed FIR filter consists of 2255 Josephson junctions(JJs)without wiring cells(i.e.,Josephson Transmission Lines(JTLs),Passive Transmission Lines(PTLs)),which is acceptable,making it possible to be used in RSFQ digital signal processors.