The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approx...The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.展开更多
传统流水线CORDIC(Coordinate Rotation Digital Computer,CORDIC)算法精度不高,输出延时较大,并且需要依靠剩余角度计算进行旋转方向的判断,占用较大的资源。针对以上问题,本文采用角度二极化重编码方法消除剩余角度计算,通过折叠角度...传统流水线CORDIC(Coordinate Rotation Digital Computer,CORDIC)算法精度不高,输出延时较大,并且需要依靠剩余角度计算进行旋转方向的判断,占用较大的资源。针对以上问题,本文采用角度二极化重编码方法消除剩余角度计算,通过折叠角度区间将角度映射于区间[0,π/4]。结合查找表以及合并迭代技术,减少角度计算的迭代次数和硬件单元,降低输出时延,只需要3个周期就能完成CORDIC计算。使用结果重映射方法完成正弦和余弦的全象限实现。寄存器资源消耗为传统算法的35.37%,输出时延减少85%。基于180nm CMOS工艺,完成CORDIC算法的ASIC实现。正弦和余弦的平均绝对误差分别为2.5472×10^(-6)、1.9396×10^(-6),相比较于传统CORDIC算法,精度提升一个数量级。展开更多
Based on the silicon-on-insulator(SOI) technology and radiation-hardened silicon gate(RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET(LDMOS) device is presented in this paper. With the g...Based on the silicon-on-insulator(SOI) technology and radiation-hardened silicon gate(RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET(LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose(TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner,and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad(Si).展开更多
随着工业技术的进步,高温高动态压力传感器的应用需求显著增加。提出一种集成专用补偿电路的高动态硅压阻式微电子机械系统(Micro-Electro-Mechanical Systems,MEMS)压力传感器,进行压力敏感芯片的结构设计和加工工艺设计,并对压力传感...随着工业技术的进步,高温高动态压力传感器的应用需求显著增加。提出一种集成专用补偿电路的高动态硅压阻式微电子机械系统(Micro-Electro-Mechanical Systems,MEMS)压力传感器,进行压力敏感芯片的结构设计和加工工艺设计,并对压力传感器进行封装和温度补偿电路设计。多层绝缘体上硅(Silicon On Insulator,SOI)材料能够使传感器在高温环境下正常工作。无引线的封装方式可有效提升传感器的频响性能。传感器后端集成了桥阻式专用集成电路(Application Specific Integrated Circuits,ASIC),能够显著减小传感器的体积,同时提升传感器整体性能。该MEMS传感器通过自动压力测试系统进行性能试验,结果表明MEMS压力传感器经过补偿后能够实现较高的线性度、稳定的零点输出特性以及理想的动态输出特性。展开更多
HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for parti...HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for particle identification and beam monitoring at HFRS. This paper presents an event-driven internal memory and synchronous readout(EDIMS)prototype ASIC chip. The aim is to provide HFRS-TPC with high-precision time and charge measurements with high count rates and a large dynamic range. The first prototype EDIMS chip integrated 16 channels and is fabricated using a 0.18-μm CMOS process. Each channel consists of a charge-sensitive amplifier, fast shaper, slow shaper, peak detect-and-hold circuit, discriminator with time-walk compensation, analog memory, and FIFO. The token ring is used for clock-synchronous readout. The chip is taped and tested.展开更多
为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来...为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来,研究能实现RS编码功能的芯片。在系统架构层,针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、消耗功耗大等问题,提出基于乘法器因子矩阵的方法对RS编码算法进行优化,通过将乘法运算转化为减法运算等方式减少数据运算量,从而降低功耗。在RTL级和门级层面,分别在逻辑综合和后端实现中加以约束来实现低功耗设计,总体功耗可以降低60%左右。解决了因IC芯片功耗过高导致芯片性能下降,从而影响芯片正常工作等问题,为集成电路工艺提供了新的发展方向。展开更多
基金support from Grant PID2020-116075GB-C21funded by MCIN/AEI/10.13039/501100011033+1 种基金by“ERDF A way of making Europe”under Grant PID2020-116075GB-C21They also acknowledge financial support from the State Agency for Research of the Spanish Ministry of Science and Innovation through the“Unit of Excellence Maria de Maeztu 2020-2023”award to the Institute of Cosmos Sciences(CEX2019-000918-M)。
文摘The BETA application-specific integrated circuit(ASIC)is a fully programmable chip designed to amplify,shape and digitize the signal of up to 64 Silicon photomultiplier(SiPM)channels,with a power consumption of approximately~1 mW/channel.Owing to its dual-path gain,the BETA chip is capable of resolving single photoelectrons(phes)with a signal-to-noise ratio(SNR)>5 while simultaneously achieving a dynamic range of~4000 phes.Thus,BETA can provide a cost-effective solution for the readout of SiPMs in space missions and other applications with a maximum rate below 10 kHz.In this study,we describe the key characteristics of the BETA ASIC and present an evaluation of the performance of its 16-channel version,which is implemented using 130 nm technology.The ASIC also contains two discriminators that can provide trigger signals with a time jitter down to 400 ps FWHM for 10 phes.The linearity error of the charge gain measurement was less than 2%for a dynamic range as large as 15 bits.
文摘传统流水线CORDIC(Coordinate Rotation Digital Computer,CORDIC)算法精度不高,输出延时较大,并且需要依靠剩余角度计算进行旋转方向的判断,占用较大的资源。针对以上问题,本文采用角度二极化重编码方法消除剩余角度计算,通过折叠角度区间将角度映射于区间[0,π/4]。结合查找表以及合并迭代技术,减少角度计算的迭代次数和硬件单元,降低输出时延,只需要3个周期就能完成CORDIC计算。使用结果重映射方法完成正弦和余弦的全象限实现。寄存器资源消耗为传统算法的35.37%,输出时延减少85%。基于180nm CMOS工艺,完成CORDIC算法的ASIC实现。正弦和余弦的平均绝对误差分别为2.5472×10^(-6)、1.9396×10^(-6),相比较于传统CORDIC算法,精度提升一个数量级。
文摘Based on the silicon-on-insulator(SOI) technology and radiation-hardened silicon gate(RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET(LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose(TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner,and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad(Si).
文摘随着工业技术的进步,高温高动态压力传感器的应用需求显著增加。提出一种集成专用补偿电路的高动态硅压阻式微电子机械系统(Micro-Electro-Mechanical Systems,MEMS)压力传感器,进行压力敏感芯片的结构设计和加工工艺设计,并对压力传感器进行封装和温度补偿电路设计。多层绝缘体上硅(Silicon On Insulator,SOI)材料能够使传感器在高温环境下正常工作。无引线的封装方式可有效提升传感器的频响性能。传感器后端集成了桥阻式专用集成电路(Application Specific Integrated Circuits,ASIC),能够显著减小传感器的体积,同时提升传感器整体性能。该MEMS传感器通过自动压力测试系统进行性能试验,结果表明MEMS压力传感器经过补偿后能够实现较高的线性度、稳定的零点输出特性以及理想的动态输出特性。
基金supported by the National Natural Science Foundation of China (Nos. 11975293 and 12105338)the Strategic Priority Research Program of Chinese Academy of Science (Nos. XDB 34040200 and XPB 23)the Technology Innovation Project of Instrument and Equipment Function Development of Chinese Academy of Sciences (No. 2023g102)。
文摘HFRS(HIAF FRagment Separator) will be the radioactive secondary beam separation line on High-Intensity heavy-ion Accelerator Facility(HIAF) in China. Several TPC detectors, with high count rates, are planned for particle identification and beam monitoring at HFRS. This paper presents an event-driven internal memory and synchronous readout(EDIMS)prototype ASIC chip. The aim is to provide HFRS-TPC with high-precision time and charge measurements with high count rates and a large dynamic range. The first prototype EDIMS chip integrated 16 channels and is fabricated using a 0.18-μm CMOS process. Each channel consists of a charge-sensitive amplifier, fast shaper, slow shaper, peak detect-and-hold circuit, discriminator with time-walk compensation, analog memory, and FIFO. The token ring is used for clock-synchronous readout. The chip is taped and tested.
文摘为解决里所(Reed-solomon,RS)编码的低功耗设计,从系统架构、RTL级、门级等不同设计层级进行分析,并在专用集成电路(Application specific integrated circuit,ASIC)设计中加以实践。基于低功耗设计将前端RTL级设计与后端IC设计结合起来,研究能实现RS编码功能的芯片。在系统架构层,针对RS编码算法中伽罗华域的乘法运算在硬件实现时存在数据运算量大、消耗功耗大等问题,提出基于乘法器因子矩阵的方法对RS编码算法进行优化,通过将乘法运算转化为减法运算等方式减少数据运算量,从而降低功耗。在RTL级和门级层面,分别在逻辑综合和后端实现中加以约束来实现低功耗设计,总体功耗可以降低60%左右。解决了因IC芯片功耗过高导致芯片性能下降,从而影响芯片正常工作等问题,为集成电路工艺提供了新的发展方向。
