Design and prototyping of the readout electronics for the transition radiation detector in the high energy cosmic radiation detection facility

The high energy cosmic-radiation detection(HERD)facility is planned to launch in 2027 and scheduled to be installed on the China Space Station.It serves as a dark matter particle detector,a cosmic ray instrument,and an observatory for high-energy gamma rays.A transition radiation detector placed on one of its lateral sides serves dual purpose,(ⅰ)calibrating HERD's electromagnetic calorimeter in the TeV energy range,and(ⅱ)serving as an independent detector for high-energy gamma rays.In this paper,the prototype readout electronics design of the transition radiation detector is demonstrated,which aims to accurately measure the charge of the anodes using the SAMPA application specific integrated circuit chip.The electronic performance of the prototype system is evaluated in terms of noise,linearity,and resolution.Through the presented design,each electronic channel can achieve a dynamic range of 0–100 fC,the RMS noise level not exceeding 0.15 fC,and the integral nonlinearity was<0.2%.To further verify the readout electronic performance,a joint test with the detector was carried out,and the results show that the prototype system can satisfy the requirements of the detector's scientific goals.

Design and evaluation of prototype readout electronics for nuclide detector in Very Large Area Space Telescope

China plans to develop the next generation dark matter particle explorer satellite,referred to as the Very Large Area Space Telescope(VLAST).As an essential step in this process,the prototype design of detectors and electronics for the VLAST is currently underway.The nuclide detector is a core detector in the VLAST.It mainly measures nuclides’charges and distinguishes high-energy gamma rays and electrons.This paper will discuss the prototype readout electronics for the VLAST’s nuclide detector,which accurately measures the charge signal of the photomultiplier tubes using the VATA160 applicationspecific integrated circuit chip;furthermore,we consider a series of critical problems,including radiation-hardening and environment monitoring.The test results show that the system exhibits stable operation,good performance,and good technical indicators.Furthermore,each electronic channel achieves a dynamic range of 0-12.5 pC,the random noise level exceeds 1.6 fC,and the integral nonlinearity exceeds 0.35%.

Prototype of the readout electronics for the RICH PID detector in the STCF

The ring imaging Cherenkov(RICH) detector for particle identification(PID) is being evaluated for the future super tau-charm facility(STCF) complex. In this work, the prototype readout electronics for the RICH PID detector is designed. The prototype RICH PID detector is based on a thick gas electron multiplier combined with a micromegas detector for Cherenkov light detection. Considering that there will be a large number(~ 690,000) of detector channels in future RICH detector, the readout electronics faces many challenges to precisely measuring time and charge information, such as reducing the noise,increasing density, and improving precision. The requirements of the readout electronics are explored, the downselection of the ASICs is made and thus a prototype readout electronics is designed and implemented. Tests are also conducted to evaluate the performance of the prototype readout electronics, and the results indicate that the time resolution is better than ~ 1 ns(RMS) when the input charge is greater than ~ 12 fC based on the APV25chip, while the time resolution is better than ~ 1 ns(RMS) at an input charge of over ~ 48 fC based on the AGET and STCF ASIC chips, and the equivalent noise charge is better than ~ 0.5 fC(RMS) @ 20 pF based on the three ASICs. The test results indicate that the prototype readout electronics design meets the requirement of the future RICH PID detector and thus provides a reference for future engineering.

Studies of an event-building algorithm of the readout system for the twin TPCs in HFRS

The High-energy Fragment Separator(HFRS),which is currently under construction,is a leading international radioactive beam device.Multiple sets of position-sensitive twin time projection chamber(TPC)detectors are distributed on HFRS for particle identification and beam monitoring.The twin TPCs'readout electronics system operates in a trigger-less mode due to its high counting rate,leading to a challenge of handling large amounts of data.To address this problem,we introduced an event-building algorithm.This algorithm employs a hierarchical processing strategy to compress data during transmission and aggregation.In addition,it reconstructs twin TPCs'events online and stores only the reconstructed particle information,which significantly reduces the burden on data transmission and storage resources.Simulation studies demonstrated that the algorithm accurately matches twin TPCs'events and reduces more than 98%of the data volume at a counting rate of 500 kHz/channel.

Proposal of the readout electronics for the WCDA in the LHAASO experiment

The LHAASO （Large High Altitude Air Shower Observatory） experiment is proposed for a very high energy gamma ray source survey, in which the WCDA （Water Cherellkov Detector Array） is one of the major coinponents. In the WCDA, a total of 3600 PMTs are placed under water in four ponds, each with a size of 150m×150 m. Precise time and cimrge measurement is required for the PMT signals, over a large signal amplitude range from a single P.E. （photo electron） to 4000 P.E. To fulfill the high requirement of a signal measurement in so many front end nodes scattered in a large area, special techniques are developed, such as multiple gain readout, hybrid transmission of clocks, commands and data, precise clock phase alignment and new trigger electronics. We present the readout electronics architecture for the WCDA and several prototype modules, which are now being testedin the laboratory.

Prototype of readout electronics for the LHAASO KM2A electromagnetic particle detectors

The KM2A （one kilometer square extensive air shower array） is the largest detector array in the LHAASO （Large High Altitude Air Shower Observatory） project. The KM2A consists of 5242 EDs （Electromagnetic particle Detectors） and 1221 MDs （Muon Detectors）. The EDs are distributed and exposed in the wild. Two channels, anode and dynode, are employed for the PMT （photomultiplier tube） signal readout. The readout electronics designed in this paper aims at accurate charge and arrival time measurement of the PMT signals, which cover a large amplitude range from 20 P.E. （photoelectrons） to 2x105 P.E. By using a ＂trigger-less＂ architecture, we digitize signals close to the PMTs. All digitized data is transmitted to DAQ （Data Acquisition） via a simplified White Rabbit protocol. Compared with traditional high energy experiments, high precision of time measurement over such a large area and suppression of temperature effects in the wild become the key techniques. Experiments show that the design has fulfilled the requirements in this project.

Clock distribution for BaF2 readout electronics at CSNS-WNS

A BaF2（Barium Fluoride） detector array is designed to precisely measure the（n, γ） cross section at the CSNS-WNS（white neutron source at China Spallation Neutron Source）. It is a 4π solid angle-shaped detector array consisting of 92 BaF2 crystal elements. To discriminate signals from the BaF2 detector, a pulse shape discrimination method is used, supported by a waveform digitization technique. There are 92 channels for digitizing. The precision and synchronization of clock distribution restricts the performance of waveform digitizing. In this paper, a clock prototype for the BaF2 readout electronics at CSNS-WNS is introduced. It is based on the PXIe platform and has a twin-stage tree topology. In the first stage, clock is synchronously distributed from the tree root to each PXIe crate through a coaxial cable over a long distance, while in the second stage, the clock is further distributed to each electronic module through a PXIe dedicated differential star bus. With the help of this topology, each tree node can fan out up to 20 clocks with 3U size. Test results show the clock jitter is less than 20 ps, which meets the requirements of the BaF2 readout electronics. Besides, this clock system has the advantages of high density, simplicity, scalability and cost saving, so it can be useful for other clock distribution applications.

Development of front-end readout electronics for silicon strip detectors

Front-end readout electronics have been developed for silicon strip detectors at our institute. In this system an Application Specific Integrated Circuit （ASIC） ATHED is used to realize multi-channel energy and time measurements. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are implemented with the CPLD. The data acquisition is carried out with a PXI-DAQ card. The software has a user-friendly GUI developed with LabWindows/CVI in the Windows XP operating system. The test results show that the energy resolution is about 1.14% for alpha at 5.48 MeV and the maximum channel crosstalk of the system is 4.60%. The performance of the system is very reliable and is suitable for nuclear physics experiments.

Design of readout electronics based on peak-holding circuit and multiplexer for a fast neutron spectrometer

Background Fast neutron detection is meaningful in many research fields such as space environment monitoring.A scintillating fiber array model for fast neutron detection was proposed and developed in 1980s.Aerospace applications of the model require electronics in small size.Purpose To design a dedicated electronic system to readout and process the 384-channel signals from scintillating fiber array,and to use the designed system to fabricate a neutron detector for aerospace applications.Methods With the method of nuclear recoil,fast neutron is detected by tracking recoil proton of n–p scatter in scintillating plastic fibers.Using the peak-holding circuits and multiplexers,the system size and power consumption were reduced.Results The detector fabricated with the designed system,had 34 cm×34 cm×27 cm mechanical size,20.4 kg weight,and 30.05W power consumption.Comparing to traditional waveform sampling electronics,the designed electronics was highly integrated and had a small size.The readout electronics also gave a better energy resolution of 39%in neutron detection,while the energy resolution was 43%in previous version.Conclusion In this study,a highly integrated readout electronic system was designed and verified.The detector using the system gave good performance.The designed electronics had potential development in fast neutron detection and other high energy physics detection system.

BESⅢ ETOF upgrade readout electronics commissioning

It is proposed to upgrade the endcap time-of-flight（ETOF） of the Beijing Spectrometer Ⅲ（BESⅢ） with a multi-gap resistive plate chamber（MRPC）, aiming at an overall time resolution of about 80 ps. After completing the entire readout electronics system, some experiments, such as heat radiation, radiation hardness and large-current beam tests, have been carried out to confirm the reliability and stability of the readout electronics. An on-detector test of the readout electronics has also been performed with the beam at the BEPCⅡ E3 line. The test results indicate that the readout electronics system fulfills its design requirements.

Design of the readout electronics for the DAMPE Silicon Tracker detector

The Silicon Tracker （STK） is one of the detectors of the DAMPE satellite used to measure the incidence direction of high energy cosmic rays. It consists of 6 X-Y double layers of silicon micro-strip detectors with 73728 readout channels. It is a great challenge to read out the channels and process the huge volume of data in the harsh environment of space. 1152 Application Specific Integrated Circuits （ASIC） and 384 ADCs are used to read out the detector channels. 192 Tracker Front-end Hybrid （TFH） modules and 8 identical Tracker Readout Board （TRB） modules are designed to control and digitalize the front signals. In this paper, the design of the readout electronics for the STK and its performance are presented in detail.

Test of a ^(3)He neutron detector readout electronics prototype for CSNS multipurpose physics neutron diffractometer

Background Large areas of 3He neutron detector array and corresponding readout electronics are used in the MPI built at China Spallation Neutron Source(CSNS)to measure the position and flight time of scattered neutrons,and MPI has a high requirement for the position resolution of 3He neutron detector.A 3He neutron detector readout electronics prototype composed of two front-end boards and one digital readout board is designed to meet the above requirements.Purpose Testing the whole readout electronics system before its mass production to ensure it can run correctly and fulfill the functional and performance requirements.Methods The test of the readout electronics prototype is implemented in the laboratory,and a signal generator is used to generate electronic signals instead of actual neutron signals.The position resolution test of the readout electronics prototype with 3He tubes is carried out in the No.20 beamline measurement room of CSNS.Results and Conclusion The functional and performance tests in the laboratory state that the readout electronics prototype can fulfill the readout requirements.The typical value of charge resolution is 0.85 fC;the integral nonlinearity of charge is 0.094%in the input charge range from 100 to 800 fC.The position resolution test result of the prototype with 3He tubes is better than the design requirement of 10 mm and also quite good compared with that of some other commercial products.These tests provide a reliable basis for the mass production of the readout electronics prototype.

Clock and data alignment scheme for readout electronics prototype of PandaX-nT

Purpose This work proposes a clock and data alignment scheme for the readout electronics system of the future PandaX-nT dark matter detection experiments.Since the waveform information of the photomultiplier signal is obtained by accumulating all acquisition channels of the front-end digitization module(FDM),it is required that each FDM acquisition channel should be synchronized.Methods The readout electronics system is composed of a clock distribution module,64 FDMs,and 4 data acquisition(DAQ)modules.The multi-board synchronous acquisition circuit can provide the same REF CLOCK and SYSREF signal for multiple FDMs boards to ensure the alignment of the sampled data collected by the analog-to-digital converter.The data aggregation circuit can ensure that the sampled data of multiple FDM boards are aligned with each other when they are aggregated to the DAQ board.Results and conclusions The functional verification test results show that the synchronization between the prototype electronics channels is less than 80 ps,thus enabling to meet the requirements of the readout electronics prototype of PandaX-nT.

Development of amulti-channel readout electronics verification system for MWDC detectors

Background The Multi-Wire Drift Chamber(MWDC)is among the significant detectors for CSR External Target Experiment(CEE).We require the MWDC detector’s front-end readout circuits to have a high integration,high count rate,and big dynamic range in order to measure the tracks of fore-angle products.Purpose In this paper,MWDC readout electronics verification system is shown,which is based on the front-end amplifier chip and Switched Capacitor Array(SCA)chip independently established by the project team.Results In the dynamic input range of 14 fC–950 fC,the readout electronics’energy measurement linearity is greater than 1%.The test results with MWDC illustrate that with a 55Fe source an energy resolution of 22.4%was acquired,and with cosmic rays the residual error is less than 400um.

Design and development of compact readout electronics with silicon photomultiplier array for a compact imaging detector

This work aims at developing compact readout electronics for a compact imaging detector module with silicon photomultiplier （SPM） array. The detector module consists of a LYSO crystal array coupling with a SensL’s 4×4 SPM array. A compact multiplexed readout based on a discretized positioning circuit （DPC） was developed to reduce the readout channels from 16 to 4 outputs. Different LYSO crystal arrays of 4×4, 8×8 and 12×12 with pixel sizes of 3.2, 1.6 and 1.0 mm respectively, have been tested with the compact readout board using a 137 Cs source. The initial results show that the compact imaging detector module with the compact multiplexed readout could clearly resolve 1 mm×1 mm×10 mm LYSO scintillation crystal array except those at the edges. The detector’s intrinsic spatial resolution up to 1 mm can be achieved with the 3 mm×3 mm size SPMArray4 through light sharing and compact multiplexed readout. Our results indicate that this detector module is feasible for the development of high-resolution compact PET.

Design and development of multi-channel front end electronics based on dual-polarity charge-to-digital converter for SiPM detector applications

With the development of silicon photomultiplier(SiPM)technology,front-end electronics for SiPM signal processing have been highly sought after in various fields.A compact 64-channel front-end electronics(FEE)system achieved by fieldprogrammable gate array-based charge-to-digital converter(FPGA-QDC)technology was built and developed.The FEE consists of an analog board and FPGA board.The analog board incorporates commercial amplifiers,resistors,and capacitors.The FPGA board is composed of a low-cost FPGA.The electronics performance of the FEE was evaluated in terms of noise,linearity,and uniformity.A positron emission tomography(PET)detector with three different readout configurations was designed to validate the readout capability of the FEE for SiPM-based detectors.The PET detector was made of a 15×15 lutetium–yttrium oxyorthosilicate(LYSO)crystal array directly coupled with a SiPM array detector.The experimental results show that FEE can process dual-polarity charge signals from the SiPM detectors.In addition,it shows a good energy resolution for 511-keV gamma photons under the dual-end readout for the LYSO crystal array irradiated by a Na-22 source.Overall,the FEE based on FPGA-QDC shows promise for application in SiPM-based radiation detectors.

FPGA-based position reconstruction method for neutron beam flux spatial distribution measurement in BNCT

A new measurement method for the spatial distribution of neutron beam flux in boron neutron capture therapy(BNCT)is being developed based on the two-dimensional Micromegas detector.To address the issue of long processing times in traditional offline position reconstruction methods,this paper proposes a field programmable gate array based online position reconstruction method utilizing the micro-time projection chamber principle.This method encapsulates key technical aspects:a self-adaptive serial link technique built upon the dynamical adjustment of the delay chain length,fast sorting,a coordinate-matching technique based on the mapping between signal timestamps and random access memory(RAM)addresses,and a precise start point-merging technique utilizing a circular combined RAM.The performance test of the selfadaptive serial link shows that the bit error rate of the link is better than 10-12 at a confidence level of 99%,ensuring reliable data transmission.The experiment utilizing the readout electronics and Micromegas detector shows a spatial resolution of approximately 1.4 mm,surpassing the current method’s resolution level of 5 mm.The beam experiment confirms that the readout electronics system can obtain the flux spatial distribution of neutron beams online,thus validating the feasibility of the position reconstruction method.The online position reconstruction method avoids traditional methods,such as bubble sorting and traversal searching,simplifies the design of the logic firmware,and reduces the time complexity from O(n2)to O(n).This study contributes to the advancement in measuring neutron beam flux for BNCT.

A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Design and testing of a miniature silicon strip detector

In this study, we developed a multi-channel lownoise electronic readout system for a silicon strip detector.Using two charge-sensitive amplifier VA140 chips from IDEAS in Norway, the system has a wide linear dynamic input range of up to 180 fC for 128 channels with 0.16 fC average equivalent noise charge. In addition, we studied the charge distribution behaviors between adjacent silicon strips with the help of transient current technology.

Development of a multi-channel readout ASIC for a fast neutron spectrometer based on GEM-TPC

A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier （GEM）-Time Projection Chamber （TPC）. Charge Amplifier and Shaping Amplifier for GEM （CASAGEM） integrates 16＋1 channels： 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board （PCB） was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.