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Additional Sensitivity Penalty of Burst Mode Receivers in Ethernet PON due to Extinction Ratio
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作者 Sub Han Ja-Won Seo +1 位作者 Tae-Whan Yoo Man-Seop Lee 《光学学报》 EI CAS CSCD 北大核心 2003年第S1期647-648,共2页
An additional sensitivity penalty of burst mode receivers due to the extinction ratio is analyzed considering the specific transmitter control in Ethernet PON. For an extinction ratio of 6dB, a penalty of 8dB occurs a... An additional sensitivity penalty of burst mode receivers due to the extinction ratio is analyzed considering the specific transmitter control in Ethernet PON. For an extinction ratio of 6dB, a penalty of 8dB occurs additionally. 展开更多
关键词 PON of Additional Sensitivity Penalty of Burst mode receivers in Ethernet PON due to Extinction Ratio in
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A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver 被引量:1
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作者 姚小城 龚正 石寅 《Journal of Semiconductors》 EI CAS CSCD 2012年第11期90-94,共5页
This paper presents a programmable gain amplifier(PGA) circuit with a digitally assisted DC offset cancellation(DCOC) scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th... This paper presents a programmable gain amplifier(PGA) circuit with a digitally assisted DC offset cancellation(DCOC) scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter(DAC) mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications. 展开更多
关键词 direct conversion receiver digital assisted DC offset cancellation segmented current mode digital-to-analog converter settling time
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Real-Time Dwell Scheduling Based on a Unified Pulse Interleaving Framework for Phased Array Radar
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作者 Ting Cheng Luqing Liu +1 位作者 Zhongzhu Li Siyu Heng 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2024年第5期1540-1553,共14页
Dwell scheduling is a key for phased array radar to realize multi-function and it becomes especially challenging in complex tactical situations.In this manuscript,a real-time radar dwell scheduling algorithm based on ... Dwell scheduling is a key for phased array radar to realize multi-function and it becomes especially challenging in complex tactical situations.In this manuscript,a real-time radar dwell scheduling algorithm based on a unified pulse interleaving framework is proposed.A unified pulse interleaving framework that can realize pulse interleaving analysis for phased array radars with different receiving modes is put forward,which greatly improves the time utilization of the system.Based on above framework,a real-time two-stage approach is proposed to solve the optimization problem of dwell scheduling.The importance and urgency criteria are guaranteed by the first pre-schedule stage,and the desired execution time criterion is improved at the second stage with the modified particle swarm optimization(PSO).Simulation results demonstrate that the proposed algorithm has better comprehensive scheduling performance than up-to-date algorithms that consider the pulse interleaving technique for both single beam and multiple beams receiving modes.Besides,the proposed algorithm can realize dwell scheduling in realtime. 展开更多
关键词 phased array radar dwell scheduling receiving mode pulse interleaving particle swarm optimization
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