A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requiremen...A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.展开更多
A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs...A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.展开更多
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University,China.
文摘A low jitter,low spur multiphase phase-locked loop（PLL） for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator（VCO） is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the loop filter bandwidth,the reference spur is suppressed. A phase noise of-118.42 dBc/Hz at a frequency offset of 1 MHz,RMS jitter of 1.53 ps and reference spur of-66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement.The chip was manufactured in 0.13μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm^2 area.
基金Project supported by the National Natural Science Foundation of China(No.61176029)the National Twelve-Five Project(No.513***)
文摘A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.
