Hardware Architecture for RSA Cryptography Based on Residue Number System

A parallel architecture for efficient hardware implementation of Rivest Shamir Adleman(RSA) cryptography is proposed.Residue number system(RNS) is introduced to realize high parallelism,thus all the elements under the same base are independent of each other and can be computed in parallel.Moreover,a simple and fast base transformation is used to achieve RNS Montgomery modular multiplication algorithm,which facilitates hardware implementation.Based on transport triggered architecture(TTA),the proposed architecture is designed to evaluate the performance and feasibility of the algorithm.With these optimizations,a decryption rate of 106 kbps can be achieved for 1 024-b RSA at the frequency of 100 MHz.

Efficient Single Event Upset-Tolerant FIR Filter Design Based on Residue Number for OBP Satellite Communication Systems

Cosmic radiation has several effects on the On-Board Processing(OBP)platform in satellite communications systems,and Single Event Upsets(SEUs)are one of its most important effects.In order to protect the Finite Impulse Response(FIR)filters against SEU,this paper proposes a novel Residue Number(RN)-based method.The proposed method applies the transpose form of the FIR filter to avoid the fault missing caused by SEU on shift registers.It also adjusts the input intelligently to avoid the fault missing caused by SEU on the filter coefficients.After all the fault missing events are avoided,the modulus can be minimised to achieve the minimum overhead.Theoretical analysis and simulation results show that the noise introduced by the input adjustment is negligible.Fault injection shows that the fault missing rate of the proposed method is zero.Finally,FPGA implementation shows that the overhead of the proposed method is approximately 75% of Triple Modular Redundancy,and is only 1%-2% higher than that of the traditional RN-based design.

A New Image Watermarking Scheme Using Genetic Algorithm and Residual Numbers with Discrete Wavelet Transform

Transmission of data over the internet has become a critical issue as a result of the advancement in technology, since it is possible for pirates to steal the intellectual property of content owners. This paper presents a new digital watermarking scheme that combines some operators of the Genetic Algorithm (GA) and the Residue Number (RN) System (RNS) to perform encryption on an image, which is embedded into a cover image for the purposes of watermarking. Thus, an image watermarking scheme uses an encrypted image. The secret image is embedded in decomposed frames of the cover image achieved by applying a three-level Discrete Wavelet Transform (DWT). This is to ensure that the secret information is not exposed even when there is a successful attack on the cover information. Content creators can prove ownership of the multimedia content by unveiling the secret information in a court of law. The proposed scheme was tested with sample data using MATLAB2022 and the results of the simulation show a great deal of imperceptibility and robustness as compared to similar existing schemes.

Elliptic Curve Point Multiplication by Generalized Mersenne Numbers

Montgomery modular multiplication in the residue number system （RNS） can be applied for elliptic curve cryptography. In this work, unified modular multipliers over generalized Mersenne numbers are proposed for RNS Montgomery modular multiplication, which enables efficient elliptic curve point multiplication （ECPM）. Meanwhile, the elliptic curve arithmetic with ECPM is performed by mixed coordinates and adjusted for hardware implementation. In addition, the conversion between RNS and the binary number system is also discussed. Compared with the results in the literature, our hardware architecture for ECPM demonstrates high performance. A 256-bit ECPM in Xilinx XC2VP100 field programmable gate array device （FPGA） can be performed in 1.44 ms, costing 22147 slices, 45 dedicated multipliers, and 8.25K bits of random access memories （RAMs）.

New Reverse Conversion for Four-Moduli Set and Five-Moduli Set

Most reverse conversions in Residue Number Systems (RNS) are based on the Chinese Remainder Theorem (CRT) and the Mixed Radix Conversion (MRC). The complexity of the circuitry of the CRT is high due to the large modulo-M operation. The MRC has a simple circuitry but it’s a sequential process in nature. The purpose of this research is to obtain an efficient reverse conversion method to reduce the computational overhead found in the conventional reverse conversion algorithms. In this paper, new algorithms for reverse conversion in RNS for four-moduli set and five-moduli set have been proposed and their correctness evaluated. Numerical evaluations to ascertain the correctness and simplicity of the algorithm have been presented. These algorithms have fewer multiplicative index operations than those in the conventional CRT and MRC. The large modulo-M operation has been eliminated which reduces the computational overhead.

Multiplier Design Utilizing Tri Valued Logic for RLNS Based DSP Applications

Residue Number System (RNS) has proved shaping the Digital Signal Processing (DSP) units into highly parallel, faster and secured entities. The computational complexity of the multiplication process for a RNS based design can be reduced by indulging Logarithmic Number System (LNS). The combination of these unusual number systems forms Residue Logarithmic Number System (RLNS) that provides simple internal architectures. Till date RLNS based processing units are designed for binary logic based circuits. In order to reduce the number of input output signals in a system, the concept of Multiple Valued Logic (MVL) is introduced in literature. In that course of research, this paper uses Tri Valued Logic (TVL) in RLNS technique proposed, to further reduce the chip area and delay value. Thus in this research work three different concepts are proposed, it includes the design of multiplier for RLNS based application for number of bits 8, 16 and 32. Next is the utilization of TVL in the proposed multiplication structure for RLNS based system along with the error correction circuits for the ternary logarithmic and antilogarithmic conversion process. Finally the comparison of the two multiplication schemes with the existing research of multiplier design for RNS based system using booth encoding concepts. It can be found that the proposed technique using TVL saves on an average of about 63% of area occupied and 97% of delay value respectively than the existing technique.

Area Efficient Sparse Modulo 2n - 3 Adder

This paper presents area efficient architecture of modulo 2n - 3 adder. Modulo adder is one of the main components for the implementation of residue number system (RNS) based applications. The proposed modulo 2n - 3 adder is implemented effectively, which utilizes parallel prefix and sparse concepts. The carries of some bits are calculated with the help of sparse approach in log2n prefix levels. This scheme is implemented with the help of idempotency property of the parallel prefix carry operator and its consistency. Parallel prefix structure contributes to fast carry computation. This will reduce area as well as routing complexity efficiently. The presented adder has double representation of residues in {0, 1, and 2}. The proposed adder offers significant reduction in area as the number of bits increases.