A variable-K trenches silicon-on-insulator(SOI)lateral diffused metal-oxide-semiconductor field-effect transistor(MOSFET)with a double conductive channel is proposed based on the enhancement of low dielectric constant...A variable-K trenches silicon-on-insulator(SOI)lateral diffused metal-oxide-semiconductor field-effect transistor(MOSFET)with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields.The device features variable-K dielectric double trenches and a P-pillar between the trenches(VK DT-P LDMOS).The low-K dielectric layer on the surface increases electric field of it.Adding a variable-K material introduces a new electric field peak to the drift region,so as to optimize electric field inside the device.Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it.Thereby,breakdown voltage(BV)of the device is increased.The double conductive channels provide two current paths that significantly reduce specific on-resistance(Ron,sp).Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm^2.The Ron,sp of VK DT-P LDMOS is reduced by 78.9%compared with the conventional structure.展开更多
A novel silicon-on-insulator（SOI） high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer（FBL） and its analytical model is analyzed in this paper.The surface heavily doped p-t...A novel silicon-on-insulator（SOI） high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer（FBL） and its analytical model is analyzed in this paper.The surface heavily doped p-top layers,interface floating buried N~＋/P~＋ layers,and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance.On the condition of ESIMOX（epoxy separated by implanted oxygen）,it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from-232 V of the conventional SOI to-425 V and the specific resistance R_（on,sp） is reduced from 0.88 to 0.2424Ω·cm^2.展开更多
基金Project supported by the Scientific Research Fund of Hunan Provincial Education Department,China(Grant No.19K001).
文摘A variable-K trenches silicon-on-insulator(SOI)lateral diffused metal-oxide-semiconductor field-effect transistor(MOSFET)with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields.The device features variable-K dielectric double trenches and a P-pillar between the trenches(VK DT-P LDMOS).The low-K dielectric layer on the surface increases electric field of it.Adding a variable-K material introduces a new electric field peak to the drift region,so as to optimize electric field inside the device.Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it.Thereby,breakdown voltage(BV)of the device is increased.The double conductive channels provide two current paths that significantly reduce specific on-resistance(Ron,sp).Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ·cm^2.The Ron,sp of VK DT-P LDMOS is reduced by 78.9%compared with the conventional structure.
基金Project supported by the National Natural Science Foundation of China(No.60906038)the National Defense Pre-Research Foundation of China(No.9140A08010308DZ02)+1 种基金the Science-Technology Foundation for Young Scientists of the University of Electronic Science and Technology of China(No.L08010301JX0830)the Department of Education of Sichuan in 2013(No.13ZA0089)
文摘A novel silicon-on-insulator（SOI） high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer（FBL） and its analytical model is analyzed in this paper.The surface heavily doped p-top layers,interface floating buried N~＋/P~＋ layers,and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance.On the condition of ESIMOX（epoxy separated by implanted oxygen）,it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from-232 V of the conventional SOI to-425 V and the specific resistance R_（on,sp） is reduced from 0.88 to 0.2424Ω·cm^2.
